DM74AS574WM ,Octal D-Type Edge Triggered Flip-Flops With 3-STATE OutputsDM74AS574 Octal D-Type Edge-Triggered Flip-Flops with 3-STATE OutputsOctober 1986Revised March 2000 ..
DM74AS640N ,Octal 3-STATE Octal Bus TransceiverFeaturesThis advanced Schottky device contains 8 pairs of 3- ■ Switching specifications at 50 pFSTA ..
DM74AS646NT ,Octal 3-STATE Bus Transceiver RegisterFeaturesThis device incorporates an octal bus transceiver and an
DM74AS574N-DM74AS574WM
Octal D-Type Edge Triggered Flip-Flops With 3-STATE Outputs
DM74AS574 Octal D-Type Edge-Triggered Flip-Flops with 3-STATE Outputs October 1986 Revised March 2000 DM74AS574 Octal D-Type Edge-Triggered Flip-Flops with 3-STATE Outputs General Description Features These 8-bit registers feature totem-pole 3-STATE outputs � Switching specifications at 50 pF designed specifically for driving highly-capacitive or rela- � Switching specifications guaranteed over full tempera- tively low-impedance loads. The high-impedance state and ture and V range CC increased HIGH-logic-level drive provide these registers � Advanced oxide-isolated, ion-implanted Schottky TTL with the capability of being connected directly to and driv- process ing the bus lines in a bus-organized system without need � Functionally equivalent with DM74S374 for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidi- � Improved AC performance over DM74S374 at approxi- rectional bus drivers, and working registers. mately half the power The eight flip-flops of the DM74AS574 are edge-triggered � 3-STATE buffer-type outputs drive bus lines directly D-type flip-flops. On the positive transition of the clock, the � Bus structured pinout Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high impedance state. In the high-imped- ance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF. The pinout is arranged to ease printed circuit board layout. All data inputs are on one side of the package while all the outputs are on the other side. Ordering Code: Order Number Package Number Package Description DM74AS574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74AS574N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 DS006314
