DM74AS286MX ,9-Bit Parity Generator/Checker With Bus-Driver Parity I/O Portapplications. The word length capability is eas-
DM74AS286M-DM74AS286MX-DM74AS286N
9-Bit Parity Generator/Checker With Bus-Driver Parity I/O Port
DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port October 1986 Revised April 2000 DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port General Description Features These universal, 9-bit parity generators/checkers utilizePNP inputs to reduce bus loading advanced Schottky high performance circuitry and featureGenerates either odd or even parity for nine data lines odd/even outputs to facilitate operation of either odd or Inputs are buffered to lower the drive requirements even parity applications. The word length capability is eas- Can be used to upgrade existing systems using MSI ily expanded by cascading. parity circuits The DM74AS286 can be used to upgrade the performance Cascadable for n-bits of most systems utilizing the DM74AS280 parity generator/ checker. Although the DM74AS286 is implemented withoutSwitching specifications at 50 pF expander inputs, the corresponding function is provided bySwitching specifications guaranteed over full the availability of an input pin XMIT. XMIT is a control line temperature and V range CC which makes parity error output active and parity an input A parity I/O portable to drive bus port when HIGH; when LOW, parity error output is inactive and parity becomes an output port. In addition, parity I/O control circuitry contains a feature to keep the I/O port in the 3-STATE during power UP or DOWN to prevent bus glitches. Ordering Code: Order Number Package Number Package Description DM74AS286M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74AS286N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Number of Inputs Parity I/O Parity Mode Error (A thru I) XMIT of that are HIGH Input Output Operation 0, 2, 4, 6, 8 N/A H L H Parity 1, 3, 5, 7, 9 N/A L L H Generator 0, 2, 4, 6, 8 H N/A H H Parity 0, 2, 4, 6, 8 L N/A H L Checker 1, 3, 5, 7, 9 H N/A H L Parity 1, 3, 5, 7, 9 L N/A H H Checker L = LOW Logic Level H = HIGH Logic Level N/A = Not Applicable © 2000 DS006305
