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DM74ALS74AM-DM74ALS74AMX-DM74ALS74AN-DM74ALS74ASJX
Dual D Positive-Edge-Triggered Flip-Flops with Preset and Clear
DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear September 1986 Revised February 2000 DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The DM74ALS74A contains two independent positive � Switching specifications at 50 pF edge-triggered flip-flops. Each flip-flop has individual D, � Switching specifications guaranteed over full tempera- clock, clear and preset inputs, and also complementary Q ture and V range CC and Q outputs. � Advanced oxide-isolated, ion-implanted Schottky TTL Information at input D is transferred to the Q output on the process positive going edge of the clock pulse. Clock triggering � Functionally and pin-for-pin compatible with Schottky occurs at a voltage level of the clock pulse and is not and LS TTL counterpart directly related to the transition time of the positive going � Improved AC performance over LS74 at approximately pulse. When the clock input is at either the HIGH or LOW half the power level, the D input signal has no effect. Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of low level signal. Ordering Code: Order Number Package Number Package Description DM74ALS74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS74ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CLK D Q Q LH X X H L HL X X L H L L X X H (Note 1) H (Note 1) HH ↑ HH L HH ↑ LL H HH L X Q Q 0 0 L = LOW State H = HIGH State X = Don't Care ↑ = Positive Edge Transition Q = Previous Condition of Q 0 Note 1: This condition is nonstable; it will not persist when preset and clear inputs return to their inactive (HIGH) level. The output levels in this condi- tion are not guaranteed to meet the V specification. OH © 2000 DS006109
