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DM74ALS652NT-DM74ALS652WM-DM74ALS652WMX Fast Delivery,Good Price
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DM74ALS652NTFAIN/a3avaiOctal 3-STATE Bus Transceiver and Register
DM74ALS652WMNATIONALN/a4avaiOctal 3-STATE Bus Transceiver and Register
DM74ALS652WMFAIN/a704avaiOctal 3-STATE Bus Transceiver and Register
DM74ALS652WMXFAIN/a221avaiOctal 3-STATE Bus Transceiver and Register


DM74ALS652WM ,Octal 3-STATE Bus Transceiver and RegisterFeaturesThis device incorporates an octal transceiver and an octal

DM74ALS652NT-DM74ALS652WM-DM74ALS652WMX
Octal 3-STATE Bus Transceiver and Register
DM74ALS652 Octal 3-STATE Bus Transceiver and Register October 1986 Revised June 2001 DM74ALS652 Octal 3-STATE Bus Transceiver and Register General Description Features This device incorporates an octal transceiver and an octalSwitching specifications at 50 pF D-type register configured to enable transmission of dataSwitching specifications guaranteed over full tempera- from bus to bus or internal register to bus. ture and V range CC This bus transceiver features totem-pole 3-STATE outputs Advanced oxide-isolated, ion-implanted Schottky TTL designed specifically for driving highly-capacitive or rela- process tively low-impedance loads. The high-impedance state and 3-STATE buffer-type outputs drive bus lines directly increased high level logic drive provide this device with the Independent registers and enables for A and B buses capability of being connected directly to and driving the bus lines in a bus organized system without need for interfaceMultiplexed real-time and stored data or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The registers in the DM74ALS652 are edge-triggered D-type flip-flops. On the positive transition of the clock (CAB or CBA), the input data is stored into the appropriate register. The CAB input controls the transfer of data into the A register and the CBA input controls the B register. The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data and a HIGH level selects stored data. The select controls have a “make before break” configuration to eliminate a glitch which would nor- mally occur in a typical multiplexer during the transition between stored and real-time data. The enable (GAB and GBA) control pins provide four modes of operation: real-time data transfer from bus A to B, real-time data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internal stored data transfer to bus A and/or B. Ordering Code: Order Number Package Number Package Description DM74ALS652WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide DM74ALS652NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2001 DS009174
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