DM74ALS646WMX ,Octal 3-STATE Bus Transceiver and RegisterDM74ALS646 Octal 3-STATE Bus Transceiver and RegisterOctober 1986Revised June 2001DM74ALS646Octal 3 ..
DM74ALS652NT ,Octal 3-STATE Bus Transceiver and Registerfeatures totem-pole 3-STATE outputs
DM74ALS646NT-DM74ALS646WM-DM74ALS646WMX
Octal 3-STATE Bus Transceiver and Register
DM74ALS646 Octal 3-STATE Bus Transceiver and Register October 1986 Revised June 2001 DM74ALS646 Octal 3-STATE Bus Transceiver and Register General Description Features This device incorporates an octal bus transceiver and anSwitching specifications at 50 pF octal D-type register configured to enable multiplexedSwitching specifications guaranteed over full tempera- transmission of data from bus to bus or internal register to ture and V range CC bus. Advanced oxide-isolated, ion-implanted Schottky TTL This bus transceiver features totem-pole 3-STATE outputs process designed specifically for driving highly-capacitive or rela- 3-STATE buffer outputs drive bus lines directly tively low-impedance loads. The high-impedance state and Multiplexed real-time and stored data increased high-logic level drive provides this device with the capability of being connected directly to and driving theIndependent registers for A and B buses bus lines in a bus-organized system without the need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidi- rectional bus drivers, and working registers. The registers in the DM74ALS646 are edge-triggered D- type flip-flops. On the positive transition of the clock (CAB or CBA), the input bus data is stored into the appropriate register. The CAB input controls the transfer of data into the A register and the CBA input controls the B register. The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data, and a HIGH level selects stored data. The select controls have a “make before break” configuration to eliminate a glitch which would nor- mally occur in a typical multiplexer during the transition between store and real-time data. The enable G and direction control pins provide four modes of operation: real-time data transfer from bus A to B, real- time data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internally stored data transfer to bus A or B. When the enable G pin is LOW, the direction pin selects which bus receives data. When the enable G pin is HIGH, both buses become disabled yet their input function is still enabled. Ordering Code Order Number Package Number Package Description DM74ALS646WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide DM74ALS646NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 DS009172
