DM74ALS645AN ,Octal Bus TransceiversDM74ALS645A Octal Bus TransceiversMarch 1987Revised February 2000DM74ALS645AOctal Bus Transceivers
DM74ALS645AN ,Octal Bus TransceiversFeaturesThese octal bus transceivers are designed for asynchro- ■ Advanced Oxide-isolated Ion-impla ..
DM74ALS645AWM ,Octal Bus TransceiversFeaturesThese octal bus transceivers are designed for asynchro- ■ Advanced Oxide-isolated Ion-impla ..
DM74ALS646NT ,Octal 3-STATE Bus Transceiver and Registerfeatures totem-pole 3-STATE outputsprocessdesigned specifically for driving highly-capacitive or re ..
DM74ALS646NT ,Octal 3-STATE Bus Transceiver and RegisterFeaturesThis device incorporates an octal bus transceiver and an
DM74ALS645AN-DM74ALS645AWM
Octal Bus Transceivers
DM74ALS645A Octal Bus Transceivers March 1987 Revised February 2000 DM74ALS645A Octal Bus Transceivers General Description Features These octal bus transceivers are designed for asynchro- � Advanced Oxide-isolated Ion-implanted Schottky TTL nous two-way communication between data busses. These process devices transmit data from the A bus to the B bus or from � Switching performance is guaranteed over full tempera- the B bus to the A bus depending upon the level at the ture and V supply range CC direction control (DIR) input. The enable input (G) can be � Switching performance specified at 50 pF used to disable the device so the busses are effectively � PNP input design reduces input loading isolated. Ordering Code: Order Number Package Number Package Description DM74ALS645AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS645AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Diagram Function Table Control Inputs Operation G DIR L L B Data to A Bus L H A Data to B Bus HX Isolation L = LOW Logic Level H = HIGH Logic Level X = Either LOW or HIGH Logic Level © 2000 DS009304
