DM74ALS640AWMX ,Inverting Octal Bus TransceiverDM74ALS640A Inverting Octal Bus TransceiverAugust 1985Revised February 2000DM74ALS640AInverting Oct ..
DM74ALS645AN ,Octal Bus TransceiversDM74ALS645A Octal Bus TransceiversMarch 1987Revised February 2000DM74ALS645AOctal Bus Transceivers
DM74ALS645AN ,Octal Bus TransceiversFeaturesThese octal bus transceivers are designed for asynchro- ■ Advanced Oxide-isolated Ion-impla ..
DM74ALS645AWM ,Octal Bus TransceiversFeaturesThese octal bus transceivers are designed for asynchro- ■ Advanced Oxide-isolated Ion-impla ..
DM74ALS646NT ,Octal 3-STATE Bus Transceiver and Registerfeatures totem-pole 3-STATE outputsprocessdesigned specifically for driving highly-capacitive or re ..
DM74ALS646NT ,Octal 3-STATE Bus Transceiver and RegisterFeaturesThis device incorporates an octal bus transceiver and an
DM74ALS640AN-DM74ALS640AWM-DM74ALS640AWMX
Inverting Octal Bus Transceiver
DM74ALS640A Inverting Octal Bus Transceiver August 1985 Revised February 2000 DM74ALS640A Inverting Octal Bus Transceiver General Description Features This inverting octal bus transceiver is designed for asyn- � Advanced Oxide-isolated Ion-implanted Schottky TTL chronous two-way communication between data busses. process This device transmits data from the A bus to the B bus or � Switching performance is guaranteed over full tempera- from the B bus to the A bus depending upon the level at the ture and V supply range CC direction control (DIR) input. The enable input (G) can be � Switching performance specified at 50 pF used to disable the device so the busses are effectively � PNP input design reduces input loading isolated. Ordering Code: Order Number Package Number Package Description DM74ALS640AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS640AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Diagram Function Table Control Inputs Operation G DIR LL B Data to A Bus LH A Data to B Bus HX Isolation L = LOW Logic Level H = HIGH Logic Level X = Either LOW or HIGH Logic Level © 2000 DS008640
