DM74ALS169BN ,Synchronous Four-Bit Up/Down Countersapplications. The DM74ALS169B is a four-bit binary up/ture and V rangeCCdown counter. The carry out ..
DM74ALS174M ,Hex/Quad D Flip-Flops with a Synchronous Clear InputDM74ALS174 • DM74ALS175 Hex/Quad D-Type Flip-Flops with ClearSeptember 1986Revised February 2000DM7 ..
DM74ALS174M ,Hex/Quad D Flip-Flops with a Synchronous Clear InputDM74ALS174 • DM74ALS175 Hex/Quad D-Type Flip-Flops with ClearSeptember 1986Revised February 2000DM7 ..
DM74ALS174M ,Hex/Quad D Flip-Flops with a Synchronous Clear InputDM74ALS174 • DM74ALS175 Hex/Quad D-Type Flip-Flops with ClearSeptember 1986Revised February 2000DM7 ..
DM74ALS174M ,Hex/Quad D Flip-Flops with a Synchronous Clear InputDM74ALS174 • DM74ALS175 Hex/Quad D-Type Flip-Flops with ClearSeptember 1986Revised February 2000DM7 ..
DM74ALS174MX ,Hex/Quad D Flip-Flops with a Synchronous Clear InputDM74ALS174 • DM74ALS175 Hex/Quad D-Type Flip-Flops with ClearSeptember 1986Revised February 2000DM7 ..
DS1816 ,3.3V EconoReset with Open Drain OutputFEATURES PIN ASSIGNMENT Automatically restarts a microprocessor after3power failureDALLASDS1816 M ..
DS1816 ,3.3V EconoReset with Open Drain OutputPIN DESCRIPTIONTO-921 RST Active Low Reset Output2 V Power SupplyCC3 GND GroundSOT-231 RST Active L ..
DS1816R-10/T&R ,3.3V EconoReset with Open Drain OutputDS18163.3V EconoReset withOpen Drain Output
DS1816R-10-U+ ,3.3V EconoReset with Open Drain OutputFEATURES PIN ASSIGNMENT Automatically restarts a microprocessor after3power failureDALLASDS1816 M ..
DS1816R-20/T&R ,3.3V EconoReset with Open Drain OutputPIN DESCRIPTIONTO-921 RST Active Low Reset Output2 V Power SupplyCC3 GND GroundSOT-231 RST Active L ..
DS1817 ,Active High 3.3V EconoResetPIN DESCRIPTIONTO-921 RST Active High Reset Output2 V Power SupplyCC3 GND GroundSOT-231 RST Active ..
DM74ALS169BM-DM74ALS169BN
Synchronous Four-Bit Up/Down Counters
DM74ALS169B Synchronous Four-Bit Up/Down Counters April 1984 Revised April 2000 DM74ALS169B Synchronous Four-Bit Up/Down Counters General Description Features These synchronous presettable counters feature an inter-Switching specifications at 50 pF nal carry look ahead for cascading in high speed countingSwitching specifications guaranteed over full tempera- applications. The DM74ALS169B is a four-bit binary up/ ture and V range CC down counter. The carry output is decoded to prevent Advanced oxide-isolated, ion-implanted Schottky TTL spikes during normal mode of counting operation. Synchro- process nous operation is provided so that outputs change coinci- Functionally and pin-for-pin compatible with Schottky dent with each other when so instructed by count enable and low power Schottky TTL counterpart inputs and internal gating. This mode of operation elimi- nates the output counting spikes which are normally asso-Improved AC performance over Schottky and low power ciated with asynchronous (ripple clock) counters. A Schottky counterparts buffered clock input triggers the four flip-flops on the rising Synchronously programmable (positive going) edge of clock input waveform. Internal look ahead for fast counting These counters are fully programmable; that is, the outputs Carry output for n-bit cascading may each be preset either HIGH or LOW. The load input Synchronous counting circuitry allows loading with carry-enable output of cas- caded counters. As loading is synchronous, setting up aESD inputs low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry permits cascading counters for n-bit synchronous applications without additional gating. Both count enable inputs (P and T) must be LOW to count. The direction of the count is determined by the level of the up/down input. When the input is HIGH, the counter counts UP; when LOW, it counts DOWN. Input T is fed forward to enable the carry outputs. The carry output thus enabled will produce a low level output pulse with a duration approxi- mately equal to the high portion of the Q output when A counting UP, and approximately equal to the low portion of the Q when counting DOWN. This low level overflow carry A pulse can be used to enable successively cascaded stages. Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. The control functions for these counters are fully synchro- nous. Changes at control inputs (enable P, enable T, load, up/down) which modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading or counting) will be dictated solely by the conditions meeting the stable setup and hold times. Ordering Code: Order Number Package Number Package Description DM74ALS169BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS169BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 DS006207
