DM74ALS165N ,8-Bit Parallel In/Serial Out Shift Registerfeatures a clock inhibit func-tion and a complemented serial output, Q .HClocking is accomplished b ..
DM74ALS169BM ,Synchronous Four-Bit Up/Down CountersFeaturesThese synchronous presettable counters feature an inter-
DM74ALS165N
8-Bit Parallel In/Serial Out Shift Register
DM74ALS165 8-Bit Parallel In/Serial Out Shift Register January 1986 Revised February 2000 DM74ALS165 8-Bit Parallel In/Serial Out Shift Register General Description Features The DM74ALS165 is an 8-bit serial register that, when � Complementary outputs clocked, shifts the data toward serial output, Q . Parallel-in H � Direct overriding load (data) inputs access to each stage is provided by eight individual direct � Gated clock inputs data inputs that are enabled by a low level at the SH/LD � Parallel-to-serial data conversion input. The DM74ALS165 also features a clock inhibit func- tion and a complemented serial output, Q . H Clocking is accomplished by a LOW-to-HIGH transition of the CLK input while SH/LD is held HIGH and CLK INH is held LOW. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a LOW CLK input and a LOW-to-HIGH transition of CLK INH will also accom- plish clocking, CLK INH should be changed to the high level only while the CLK input is HIGH. Parallel loading is inhibited when SH/LD is held HIGH. The parallel inputs to the register are enabled while SH/LD is LOW indepen- dently of the levels of CLK, CLK INH, or SER inputs. Ordering Code: Order Number Package Number Package Description DM74ALS165M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Internal Shift/ Clock Clock Serial Parallel Outputs Output A...H Q Q Q Load Inhibit A B H L X X X a...h a b h HL L X X Q Q Q A0 B0 H0 HL ↑ HX HQ Q An Gn HL ↑ LX LQ Q An Gn H ↑ LH X H Q Q An Gn H ↑ LL X L Q Q An Gn HH X X X Q Q Q A0 B0 H0 H = HIGH Level (steady-state), L = LOW Level (steady-state) X = Don't Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively Q , Q , Q = The level of Q , Q , or Q , respectively, before the A0 B0 H0 A B H indicated steady-state input conditions were established Q , Q = The level of Q or Q , respectively, before the most recent An Gn A G ↑ transition of the clock © 2000 DS006712
