DM74ALS162BN ,Synchronous Four-Bit Decade Counter with Synchronous ClearDM74ALS161B • DM74ALS162B • DM74ALS163B Synchronous Four-Bit CounterApril 1984Revised February 2000 ..
DM74ALS163BM ,Synchronous Four-Bit Binary Counter with Synchronous ClearGeneral Descriptioncounters for n bit synchronous application without addi-These synchronous preset ..
DM74ALS163BN ,Synchronous Four-Bit Binary Counter with Synchronous ClearGeneral Descriptioncounters for n bit synchronous application without addi-These synchronous preset ..
DM74ALS165N ,8-Bit Parallel In/Serial Out Shift Registerfeatures a clock inhibit func-tion and a complemented serial output, Q .HClocking is accomplished b ..
DM74ALS169BM ,Synchronous Four-Bit Up/Down CountersFeaturesThese synchronous presettable counters feature an inter-
DM74ALS161BM-DM74ALS161BMX-DM74ALS161BN-DM74ALS162BN-DM74ALS163BM-DM74ALS163BN
Synchronous Four-Bit Binary Counter with Asynchronous Clear
DM74ALS161B • DM74ALS162B • DM74ALS163B Synchronous Four-Bit Counter April 1984 Revised February 2000 DM74ALS161B • DM74ALS162B • DM74ALS163B Synchronous Four-Bit Counter The carry look ahead circuitry provides for cascading General Description counters for n bit synchronous application without addi- These synchronous presettable counters feature an inter- tional gating. Instrumental in accomplishing this function nal carry look ahead for application in high speed counting are two count enable inputs (P and T) and a ripple carry designs. The DM74ALS162B is a four-bit decade counter, output. Both count enable inputs must be HIGH to count. while the DM74ALS161B and DM74ALS163B are four-bit The T input is fed forward to enable the ripple carry output. binary counters. The DM74ALS161B clears asynchro- The ripple carry output thus enabled will produce a high nously, while the DM74ALS162B and DM74ALS163B clear level output pulse with a duration approximately equal to synchronously. The carry output is decoded to prevent the high level portion of QA output. This high level overflow spikes during normal counting mode of operation. Synchro- ripple carry pulse can be used to enable successive cas- nous operation is provided by having all flip-flops clocked caded stages. HIGH-to-LOW level transitions at the enable simultaneously so that outputs change coincident with P or T inputs of the DM74ALS161B through each other when so instructed by count enable inputs and DM74ALS163B may occur regardless of the logic level on internal gating. This mode of operation eliminates the out- the clock. put counting spikes which are normally associated with The DM74ALS161B through DM74ALS163B feature a fully asynchronous (ripple clock) counters. A buffered clock independent clock circuit. changes made to control inputs input triggers the four flip-flops on the rising (positive- (enable P or T, or load) that will modify the operating mode going) edge of the clock input waveform. will have no effect until clocking occurs. The function of the These counters are fully programmable, that is, the outputs counter (whether enabled, disabled, loading or counting) may be preset to either level. As presetting is synchronous, will be dictated solely by the conditions meeting the stable setting up a low level at the load input disables the counter set-up and hold times. and causes the outputs to agree with set up data after the next clock pulse regardless of the levels of enable input. Features LOW-to-HIGH transitions at the load input are perfectly � Switching specifications at 50 pF acceptable regardless of the logic levels on the clock or enable inputs. � Switching specifications guaranteed over full tempera- ture and V range The DM74ALS161B clear function is asynchronous. A low CC level at the clear input sets all four of the flip-flop outputs � Advanced oxide-isolated, ion-implanted Schottky TTL LOW regardless of the levels of clock, load or enable process inputs. These two counters are provided with a clear on � Functionally and pin-for-pin compatible with Schottky power-up feature. The DM74ALS162B and DM74ALS163B and low power Schottky TTL counterpart clear function is synchronous; and a low level at the clear � Improved AC performance over Schottky and low power input sets all four of the flip-flop outputs LOW after the next Schottky counterparts clock pulse, regardless of the levels of enable inputs. This synchronous clear allows the count length to be modified � Synchronously programmable easily, as decoding the maximum count desired can be � Internal look ahead for fast counting accomplished with one external NAND gate. The gate out- � Carry output for n-bit cascading put is connected to the clear input to synchronously clear � Synchronous counting the counter to all low outputs. LOW-to-HIGH transitions at the clear input of the DM74ALS162B and DM74ALS163B � Load control line are also permissible regardless of the levels of logic on the � ESD inputs clock, enable or load inputs. Ordering Code: Order Number Package Number Package Description DM74ALS161BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS161BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74ALS162BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS162BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74ALS163BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS163BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 DS006206
