DM74ALS125N ,Quad 3-STATE BufferDM74ALS125 Quad 3-STATE BufferNovember 1989Revised February 2000DM74ALS125Quad 3-STATE Buffer
DM74ALS133M ,13-Input NAND GateDM74ALS133 13-Input NAND GateFebruary 1991Revised February 2000DM74ALS13313-Input NAND Gate
DM74ALS133M ,13-Input NAND GateFeaturesThis device contains a single gate, which performs the ■ Switching specifications at 50 pFl ..
DM74ALS133N ,13-Input NAND GateFeaturesThis device contains a single gate, which performs the ■ Switching specifications at 50 pFl ..
DM74ALS137MX ,3-Line to 8-Line Decoder/Demultiplexer with Address LatchesDM74ALS137 3 to 8 Line Decoder/Demultiplexer with Address LatchesFebruary 1991Revised February 2000 ..
DM74ALS137N ,3-Line to 8-Line Decoder/Demultiplexer with Address LatchesFeaturesThe ALS137 is a three line to eight line decoder/demulti- ■ Combines decoder and 3-bit addr ..
DS1812R-5/T&R ,5V EconoReset with Active High Push-Pull OutputDS18125V EconoReset with ActiveHigh Push-Pull Output
DS1812R-5-U+ ,5V EconoReset with Active High Push-Pull OutputFEATURES PIN ASSIGNMENT Automatically restarts a microprocessor after3power failureDALLASDS1812 M ..
DS1813 ,5V EconoReset with PushbuttonPIN DESCRIPTION Monitors Pushbutton for External Override PIN NAME FUNCTION Maintains Reset for T ..
DS1813-10 ,5V EconoReset with PushbuttonDS18135V EconoReset with Pushbuttonwww.dalsemi.com
DS1813-10 ,5V EconoReset with PushbuttonFEATURES PIN ASSIGNMENT Automatically restarts a microprocessor after3power failure Monitors push ..
DS1813-10+ ,5V EconoReset with PushbuttonPIN DESCRIPTION Monitors Pushbutton for External Override PIN NAME FUNCTION Maintains Reset for T ..
DM74ALS125M-DM74ALS125MX-DM74ALS125N
Quad 3-STATE Buffer
DM74ALS125 Quad 3-STATE Buffer November 1989 Revised February 2000 DM74ALS125 Quad 3-STATE Buffer General Description Features This device contains four independent gates each of which �Advanced low power oxide-isolated ion-implanted performs a non-inverting buffer function. The outputs have Schottky TTL process the 3-STATE feature. The 3-STATE circuitry contains a fea- � Functional and pin compatible with the 74LS counterpart ture that maintains the buffer outputs in 3-STATE (high � Switching response specified into 500Ω and 50 pF load impedance state) during power supply ramp-up or ramp- � Switching response specifications guaranteed over full down. This eliminates bus glitching problems that arise temperature and V supply range CC during power-up and power-down. To minimize the possi- bility that two outputs will attempt to take a common bus to � PNP input design reduces input loading opposite logic levels, the disable time is shorter than the � Low level drive current: 74ALS = 24 mA enable time of the outputs. Ordering Code: Order Number Package Number Package Description DM74ALS125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS125N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Diagram Functional Table Y = A Input Output AC Y LL L HL H X H Hi-Z H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level Hi-Z = 3-STATE (Outputs are disabled) © 2000 DS010620
