DM74ALS109AMX ,Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and ClearDM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and ClearApril 1984Revised Febru ..
DM74ALS109AN ,Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and ClearDM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and ClearApril 1984Revised Febru ..
DM74ALS10AM ,Triple 3-Input NAND GatesFeaturesThis device contains three independent gates, each of ■ Switching specifications at 50 pFwh ..
DM74ALS10AMX ,Triple 3-Input NAND GatesFeaturesThis device contains three independent gates, each of ■ Switching specifications at 50 pFwh ..
DM74ALS10AMX ,Triple 3-Input NAND GatesFeaturesThis device contains three independent gates, each of ■ Switching specifications at 50 pFwh ..
DM74ALS10AN ,Triple 3-Input NAND GatesFeaturesThis device contains three independent gates, each of ■ Switching specifications at 50 pFwh ..
DS1811R-5-U+ ,5V EconoReset with Open Drain OutputPIN DESCRIPTIONTO-921 RST Active Low Reset Output2 V Power SupplyCC3 GND GroundSOT-231 RST Active L ..
DS1812-10 ,5V EconoReset with Active High Push-Pull OutputPIN DESCRIPTIONTO-921 RST Active High Reset Output2 V Power SupplyCC3 GND GroundSOT-231 RST Active ..
DS1812-5 ,5V EconoReset with Active High Push-Pull OutputFEATURES PIN ASSIGNMENT Automatically restarts a microprocessor after3power failure Maintains res ..
DS1812-5+ ,5V EconoReset with Active High Push-Pull OutputPIN DESCRIPTIONTO-921 RST Active High Reset Output2 V Power SupplyCC3 GND GroundSOT-231 RST Active ..
DS1812R-5/T&R ,5V EconoReset with Active High Push-Pull OutputDS18125V EconoReset with ActiveHigh Push-Pull Output
DS1812R-5-U+ ,5V EconoReset with Active High Push-Pull OutputFEATURES PIN ASSIGNMENT Automatically restarts a microprocessor after3power failureDALLASDS1812 M ..
DM74ALS109AM-DM74ALS109AMX-DM74ALS109AN
Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear
DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear April 1984 Revised February 2000 DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The DM74ALS109A is a dual edge-triggered flip-flop. Each � Switching specifications at 50 pF flip-flop has individual J, K, clock, clear and preset inputs, � Switching specifications guaranteed over full tempera- and also complementary Q and Q outputs. ture and V range CC Information at input J or K is transferred to the Q output on � Advanced oxide-isolated, ion-implanted Schottky TTL the positive going edge of the clock pulse. Clock triggering process occurs at a voltage level of the clock pulse and is not � Functionally and pin for pin compatible with Schottky directly related to the transition time of the positive going and LS TTL counterpart pulse. When the clock input is at either the HIGH or LOW � Improved AC performance over LS109 at approximately level, the J, K input signal has no effect. half the power Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of low level signal. The J-K design allows operation as a D flip-flop by tying the J and K inputs together. Ordering Code: Order Number Package Number Package Description DM74ALS109AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS109AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CK J K QQ LH X X X H L HL X X X L H L L X X X H (Note 1) H (Note 1) HH ↑ LL L H HH ↑ H L TOGGLE HH ↑ LH Q Q 0 0 HH ↑ HH H L HH L X X Q Q 0 0 L = LOW State H = HIGH State X = Don't Care ↑ = Positive Edge Transition, Q = Previous Condition of Q 0 Note 1: This condition is nonstable; it will not persist when present and clear inputs return to their inactive (HIGH) level. The output levels in this condition are not guaranteed to meet the V specification. OH © 2000 DS006196
