DM7442AN ,BCD to Decimal DecodersFeaturesThese BCD-to-decimal decoders consist of eight inverters Diode clamped inputsand ten, four ..
DM7442AN ,BCD to Decimal DecodersFeaturesYDiode clamped inputsThese BCD-to-decimal decoders consist of eight invertersYand ten, four ..
DM7445N , BCD to Decimal Decoder/DriverFeaturesYFull decoding of input logicThese BCD-to-decimal decoders/drivers consist of eight in-Yver ..
DM7447AN , BCD to 7-Segment Decoder/Driver with Open-Collector OutputsDM7446A, DM7447A BCD to 7-Segment Decoders/DriversSeptember 1986Revised February 2000DM7446A, DM744 ..
DM7447AN , BCD to 7-Segment Decoder/Driver with Open-Collector OutputsDM7446A, DM7447A BCD to 7-Segment Decoders/DriversSeptember 1986Revised February 2000DM7446A, DM744 ..
DM7451N ,7 V, dual 2-wide 2-input AOI gateGeneral Description
This device contains two independent combinations of
gates, each of which ..
DS1747WP-120 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION A0–A18 – Address Input CE – Chip Enable OE – Output Enable WE – Write Enable V ..
DS1747WP-120+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMs DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DS1747WP-C2+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Cont ..
DS17485-5 , Real-Time Clocks
DS17485E3 ,3V/5V Real-Time Clockfeatures: PWR CC X1 23SQW2Y2K compliant VBAUXX2 3 22+3V or +5V operation 4 21 RCLRAD0 SMI re ..
DS17485S-5 ,3V/5V Real-Time ClockFEATURES PIN ASSIGNMENT Incorporates industry standard DS1287 PC clock 1 24 V plus enhanced
DM7442AN
PIP Controller
DM7442A BCD to Decimal Decoder August 1986 Revised February 2000 DM7442A BCD to Decimal Decoder General Description Features These BCD-to-decimal decoders consist of eight inverters � Diode clamped inputs and ten, four-input NAND gates. The inverters are con- � Also for application as 4-line-to-16-line decoders; nected in pairs to make BCD input data available for 3-line-to-8-line decoders decoding by the NAND gates. Full decoding of input logic � All outputs are high for invalid input conditions ensures that all outputs remain off for all invalid (10–15) � Typical power dissipation 140 mW input conditions. � Typical propagation delay 17 ns Ordering Code: Order Number Package Number Package Description DM7442AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 DS006516
