DM7438MX , Quad 2-Input NAND Buffer with Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains four independent gates each of w ..
DM7438N ,7 V, quad 2-input NAND buffer with open-collector outputGeneral Description Pull-Up Resistor Equations
This device contains four independent gates each of ..
DM7439N ,DM7439 Quad 2-Input NAND Buffer with Open-Collector OutputDM7439Quad2-InputNANDBufferwithOpen-CollectorOutputAugust1989DM7439Quad2-InputNANDBufferwithOpen-Co ..
DM7440N ,7 V, dual 4-input NAND bufferGeneral Description
This device contains two, 4 input gates that perform the
Logic NAND functio ..
DM7442AN ,BCD to Decimal DecodersFeaturesThese BCD-to-decimal decoders consist of eight inverters Diode clamped inputsand ten, four ..
DM7442AN ,BCD to Decimal DecodersFeaturesYDiode clamped inputsThese BCD-to-decimal decoders consist of eight invertersYand ten, four ..
DS1747W-120+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Cont ..
DS1747W-120+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Cont ..
DS1747W-120IND ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION A0–A18 – Address Input CE – Chip Enable OE – Output Enable WE – Write Enable V ..
DS1747WP-120 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION A0–A18 – Address Input CE – Chip Enable OE – Output Enable WE – Write Enable V ..
DS1747WP-120+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMs DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DS1747WP-C2+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Cont ..
DM7438MX
Quad 2-Input NAND Buffer with Open-Collector Outputs
DM7438 • 7438 Quad 2-Input NAND Buffers with Open-Collector Outputs September 1986 Revised February 2000 DM7438 • 7438 Quad 2-Input NAND Buffers with Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains four independent gates each of which performs the logic NAND function. The open-collector out- puts require external pull-up resistors for proper logical operation. Where: N (I ) = total maximum output high current 1 OH for all outputs tied to pull-up resistor N (I ) = total maximum input high current for 2 IH all inputs tied to pull-up resistor N (I ) = total maximum input low current for 3 IL all inputs tied to pull-up resistor Ordering Code: Order Number Package Number Package Description DM7438M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM7438N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 7438SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = AB Inputs Output AB Y LL H LH H HL H HH L H = HIGH Logic Level L = LOW Logic Level © 2000 DS006513
