DM74181N ,ARITHMETIC LOGIC UNIT/FUNCTION GENERATORSFeatures
I Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magni ..
DM74181N ,ARITHMETIC LOGIC UNIT/FUNCTION GENERATORSapplications data for the DM54S182.
(Continued)
Connection Diagram Pin Designations
Dual-ln-Line ..
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DM74191N ,Synchronous Up/Down 4-Bit Binary Counter with Mode ControlapplicationsThe clock, down/up, and load inputs are buffered to lowerYAlternate Military/Aerospace ..
DM74191N ,Synchronous Up/Down 4-Bit Binary Counter with Mode ControlFeaturesYSingle down/up count control lineThis counter is fully programmable; that is, the outputs ..
DS1744W-120+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail C ..
DS1744W-120IND ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION A0–A14 - Address Input CE - Chip Enable OE - Output Enable WE - Write Enable V ..
DS1744W-120IND+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION A0–A14 - Address Input CE - Chip Enable OE - Output Enable WE - Write Enable V ..
DS1744WP+120 ,Y2K-Compliant, Nonvolatile Timekeeping RAMs DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DS1744WP-120 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail C ..
DS1744WP-120+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail C ..
DM74181N
ARITHMETIC LOGIC UNIT/FUNCTION GENERATORS
Ri?"' National
Semiconductor
DM54181
Arithmetic Logic Unit/Function Generators
General Description Features
These arithmetic logic units (ALU)/tunction generators per- ll Arithmetic operating modes:
form 16 binary arithmetic operations on two 4-bit words, as Addition
shown in Tables I and I1. These operations are seiected by Subtraction
the four function-seiect lines (SO, St, S2, S3) and include
addition, subtraction, decrement, and straight transfer.
When performing arithmetic manipulations, the internal car-
ries must be enabled by applying a low-levet voltage to the
mode control input (M). A full carry look-ahead scheme is
available in these devices for fast, simultaneous carry gen-
eration by means of two cascade-outputs (P and G) for the
four bits in the package. When used in conjunction with the
DM54S182 full carry look-ahead circuits, high-speed arith-
metic operations can be performed. The typical addition
times shown below illustrate how little time is required for
addition of longer words, when full carry look-ahead is em-
ployed. The method of cascading 182 circuits with these
ALU's to provide multi-level full carry look-ahead is illustrat-
ed under typical applications data for the DM54S182.
Shift operand A one position
Magnitude comparison
Plus twelve other arithmetic operations
I: Logic function modes:
EXCLUSIVE-OR
Comparator
AND, NAND, OR, NOR
Plus ten other logic operations
l: Full look-ahead for high-speed operations on long
(Continued)
Connection Diagram Pin Designations
Dual-ln-Line Package Designation Pln Nos. Function
'" INPuTs j r ou'fu's " A3,A2,A1, A0 19, 21,23, 2 WordA Inputs
"t T 8" T T t 'i' T°n+4 i' A--B t B3, B2, BI,BO 18, 20, 22.1 WordBlnputs
24 23122 2tl20l19lt8l1rr6 151413 -_
M, S2, S1, so 3. 4,5,6 Function Select
Inputs
On 7 Inv. Carry Input
M 8 Mode Control
F3, F2, F1, F0 13, 11, 10, 9 Function Outputs
A TAT B 14 ComparatorOutput
Carry Propagate
I1 " a 4 s 6 7 8 " I10 '11 l" Cn+4 16 Inv.CarryOutput
BO AO S3 s2 St so on M F0 Ft F2 GND G 17 Carry Generate
L v " L 4 Output
INPUTS OUTPUTS
TL/F/6560-1 V00 24 Supply Voltage
Order Number DM54181J GND 12 Ground
See NS Package Number J24A
Number Package Count Carry Method
Typical
of Addition Times Arithmetic] Look Ahead Betwgen
Bits Logle Units Carry Generators ALU 3
1 to4 20 ns 1 0 None
5 to 8 30 ns 2 0 Ripple
9 to 16 30 ns 3 or 4 1 Full Look-Ahead
17 to 64 50 ns 5 to 16 2 to 5 Full Look-Ahead
Material Copyrighted By Its Respective Manufacturer
Absolute Maximum Ratings (Note)
If MIIItary/Aerospace speclfled devices are required,
please contact the National Semiconductor Sales
offltte/Dltgtrittutorts for avallablllty and speclflcatlons.
Supply Voltage 7V
Input Voltage 5.5V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran-
teed. The dew'ce should not be opera red at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Opera ting Conditions " table will define
Output Voltage (A --- B Output)
Operating Free Air Temperature Range
Storage Temperature Range
- 55°C to + 125°C
-65t to +150°C
Recommended Operating Conditions
the conditions for actual device operation.
Symbol Parameter DM54181 Unlts
Min Nom Max
Vcc Supply Voltage 4.5 5 5.5 V
" High Level Input Voltage 2 V
" Low Level Input Voltage 0.8 V
VOH High Level Output 5 5 V
Voltage (A = B Output) .
IOH li,t2,'t11'lfte't,tt A = B) --800 “A
'OL Low Level Output Current 16 mA
TA 1r,t,1irracli,T1tir'"1 --55 125 "C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min oJ2'n Max Units
V. InputClamp Voltage Vcc == Min, l. = --12 mA -1.5 V
ICEX High Level Output Vcc = Min, vo = 5.5V 250 A
Current (A = B Output) " = Max, Ihr, = Min "
VOH High Level Output Vcc == Min, IOH -- Max 2 4 V
Voltage (All ExceptA = B) " = Max, VIH = Min .
VOL Low Level Output Vcc = Min, IOL = Max 0 4 V
Voltage Ihr, = Min, " = Max .
h Input Current @ Max VCC = Max, V. = 5.5V 1 mA
Input Voltage
IIH High Level input VCC = Max Mode 40
Current V] --- 2.4V A or B 120 p1A
Carry 200
lit. Low Level Input VCC = Max Mode --1.6
Current V. = 0.4V -
A or B 4.8 m A
S -6.4
Carry -8
los Short Circuit Output VCC --- Max _ -
Current (All ExceptA -- B) V. = 2.4V 20 55 mA
ICCH Supply Current with Vcc = Max
Outputs High (Note 3) 88 127 mA
'CCL Supply Current with Vcc = Max
Outputs Low (Note 4) 92 135 mA
Not. lt All typicals are at Vcc - 5V, TA = 25'0.
Note 2: Not more than one output should be shorted at a tlme.
Not. & log“ Is measured with SO through S3. M, and A inputs at 4.6V, all other inputs grounded and all outputs open.
Note 4: IOCL is measured with SO through 33 and M inputs at 4.5V. all other inputs grounded and all outputs open.
This Material Copyrighted By Its Respective Manufacturer
Switchlng Characteristics Vcc = 5V, TA = 25'0 (See Section1 for Test Waveforms and Output Load)
DM541B1
From To
ttl P t l I == .--.
Symb arame er (Input) (Output) Gond t on: RL 4000, th. " pF Units
Mln Max
tpLH Propagation Delay Time, 18
Low-to-High Level Output Cn G, + 4 ns
tpHL Propagation Delay Time, 19
High-to-Low Level Output
tpLH Propagation Delay Time, M = ov, SO = 30
Low-to-High Level Output AnyA C + 4 $3 -- 4.5V ns
tpHL Propagation Delay Time, or B ik-r-,- S2 g 0V 33
High-to-Low Level Output ( mo e)
1PLH Propagation Delay Time, M = 0V, SO = 30
Low-to-High Level Output AnyA S3 = 0V
B %+4 S1---S2=c4.5V m
tpHL Propagation Delay Time, or WEE cg . 33
High-to-Low Level Output ( m o)
[pm Propagation Delay Time, M = ov 19
Low-to-High Level Output G, Any F SUV or ns
tpHL Propagation Delay Time, DIFF mode) 18
High-to-Low Levet Output
tpLH Propagation Delay Time, M = 0V, so = 19
Low-to-High Level Output Any A G S3 = 4.5V ns
tpHL Propagation Delay Time, or B 'll-i-, S2 (1: 0V 19
High-to-Low LevelOutput ( mo e)
mm Propagation Delay Time, M == ov, so = 20
Low-to-High Level Output Any A G S3 = 0V ns
tpHL Propagation Delay Time, or B 501;: S2 = 4.5V 25
High-to-Low Level Output ( mods)
1pLH Propagation Delay Time, M = ov, so = 19
Low-to-High Level Output Any A P S3 = 4.5V ns
tpHL Propagation Delay Time, or B ik-ri, Sit i ov 25
High-to-Low Level Output ( mo ts)
tpLH Propagation Delay Time, M = ov, S = 25
Low-to-High Level Output Any A P S3 = 0V ns
tPHL Propagation Delay Time, or B ii-Gi- S2 i, 4 5V 25
High-to-Low Level Output ( mo 9)
tpLH Propagation Delay Time, M = ov, so = 30
Low-to-High Level Output A or Bi Fi S3 = 4 5V ns
tPHL Propagation Delay Time, lla, S2 d: ov 30
High-to-Low Level Output ( mo ts)
tpLH Propagation Delay Time, M = 0V, so = 24
Low-to-High Level Output Ai or Bi Fi S3 = 0V n s
. . SI = S2 = 4.5V
tpHL Propagation Delay Time, W d 24
High-to-Low Level Output ( mo o)
tpLH Propagation Delay Time, 28
Low-to-High Level Output Ai or Bi F; M = 4.5V ns
tpHL Propagation Delay Time, (logic mode) 30
High-to-Low Level Output
tpLH Propagation Delay Time, M = ov, so = 40
Low-to-High Level Output AnyA A = B sa = 0V ns
tPHL Propagation Delay Time, or B 'g-Si- S2 d: 4.5V 40
High-to-Low Level Output ( mo e)
This Material Copyrighted By Its Respective Manufacturer
General Description (Continued)
It high speed is not important, a rippie-carry input (On) and a
ripple-carry output (Cn+4) are available. However, the rip-
ple-carry delay has also been minimized so that arithmetic;
manipulations for small word lengths can be performed
without external circuitry.
These circuits will accommodate active-high or active-iow
data, if the pin designations are interpreted as shown below.
Subtraction is accomplished by I's complement addition,
where the 1's complement of the subtrahend is generated
internally. The resultant output is A-B-I, which requires
an end-around or forced carry to provide A-B.
The 181 can also be utilized as a comparator. The A = B
output is internally decoded from the function outputs (F0,
F1, F2, F3) so that when two words of equal magnitude are
applied at the A and B inputs, it will assume a high level to
indicate equality (A = B), Tho ALU should be in the subtract
mode with Cn = H when performing this comparison. The A
== B output is open-coliector so that it can be wire-AND
connected to give a comparison for more than four bits.
The carry output (Cn+ 4) can also be used to supply
relative magnitude information. Again, tho ALU should be
placed in tho subtract mode by placing the function select
inputs ss, Stl, S1, so at L, H, H, L, respectively.
These circuits have been designed to not only incorporate
all of the designer's requirements for arithmetic operations,
but also to provide 16 possible functions of two Boolean
variables without the use of external circuitry. These logic
functions are selected by use of the four tunction-select in-
puts (SO, SI, Sit, S3) with the mode-control input (M) at a
high level to disable the internal carry. The 16 logic func-
tions are detailed in Tables 1 and 2 and include exclusive-
OR, NAND, AND, NOR, and OR functions
ALU SIGNAL DESIGNATIONS
The DM54181 can be used with the signal designations of
either Figure 1 or Figure 2.
The logic tunctions and arithmetic operations obtained with
signal designations as in Figure t are given in Table I; those
obtained with the signal designations of Figure 2 are given
in Table II.
Pin Number 2 1 23 22 21 20 19 " 9 10 " 13 7 16 15 "
Active-High Data (T able I) A0 BO A1 B1 A2 B2 A3 B3 F0 F 1 F2 F3 Ur, c,, +4 X Y
Active-Low Data (Table II) Ao BO AI B1 Att B2 M BS po Pt F2 :3 on th + 4 p 5
Input Output Active-ngh Data Jutthte-Low Data
Cn th, + 4 (Figure 1) (Figure 2)
H H As B A2 B
H L A > B A < B
L H A < B A> B
L L A2 B A s B
This Material Copyrighted By Its Respective Manufacturer
General Description (Continued)
(2) (1) (23) (22) (21) (20) (19) (18) (2) (1) (23) (22) (21) (20) (19) (18)
A0 BO At 31 A2 B2 A3 Ba Att BO AN B1 A2 " A3 "
tr)--er-o Ca m On
181 A = B -it4) 181 A = B »_..(1‘)
(8) M (B) In
so F1 F2 F3 cn+4 v x F0 F1 F2 " Cn+4 G P
W) (10) (11) (13) us) (17 (15) (9) (10) (11) (13) (1o) " (15)
tartutum nnnm 6)W) 9)“H0¢m nnnm 5)m
" x0 V1 x1 " " " x3 GO PO Gt PI G2 " G3 P3
tt '---m P 0-0)
(150 Cn 8182 t13) Ch 5132
v -t10) G O-tto;
cn+x cn'l-y Ch+e c"+" Ch+r c047
(12) (11) J, (12) (11) m
TLlF/6560-2 TL/F/6SBO-3
FIGURE 1 FIGURE 2
TABLEI
Selectlon Active High Data
M = H M = L;Artthrmttlc Operations
S3 S2 SI SO Funcilons Cn = H(no carry) th, -- L twith carry)
L L L L Fr---A F=A F----APlus1
L L L H F=A+B F=A+B F=(A+B)Plus1
L L H L F=Ka F--A+B F=m+EMw1
L L H H F = 0 F = Minus1 (2's Compl) F = Zero
L H L L F--ATS F=APlusA§ F=APIusA§PIus1
L H L H F--tT F=--tA-rB)PtusAA F=(A+B)PIusA§PIus1
L H H L F=AeB F=AMinusBMinus1 F=AMinusB
L H H H F---M F=A§Minus1 F---AA
H L L L F--A+B F=APlusAB F=APIusABPlus1
H L L H F--AOB F=APlusB F=APlusBPlus1
H L H L F=B F---tA+A)PtusAB F=(A+§)PIusABPIus1
H L H H F=AB F=ABMinusI F=AB
H H L L F=1 Fr-=APlusA* F=APIusAPlus1
H H L H F=A+§ F=(A+B)PlusA F=(A+B)PlusAPlus1
H H H L F=A+B F=(A+§)PlusA F---(A+QPlusArnust
H H H H F=A F=AMinus1 F=A
"Each bit is shifted to the next more significant position.
This Material Copyrighted By Its Respective Manufacturer
General Description (Continued)
TABLE II
Selectlon Active Low Data
M = H M 'at" L; Arlthmetlc Operatlons
S3 " St SO Functlons th, = L (no carry) on --- H (wlth carry)
L L L L F---R F==AMinus1 F=A
L L L H F--ritT F=ABMinus1 F=AB
L L H L F---A+B F--AAMinusI F--AB
L L H H F = 1 F = Minus1 W's Compl) F = Zero
L H L L F=A+B F=APlus(A+§) F=APlus(A+§)Plus1
L H L H F--A F=ABPIus(A+B) F=ABPIus(A+§)Plus1
L H H L F.---AeB F=AMinusBMinus1 F=AMinusB
L H H H F--A+B F---A+A F=(A+§)Plus1
H L L L F--AB F---APlus(A+B) F=APIus(A+B)PIus1
H L L H F=AeB F=AP1usB F=APlusBPlus1
H L H L F---B F---ABPiusiA+B) F---AtTPtus(A+B)Plus1
H L H H F=A+B F=A+B F=(A+B)Plus1
H H L L F=0 F--APlusA* F=APlusAPlus1
H H L H F = AA F = AB PlusA F --- AB PIusAPIus1
H H H L F = AB F = Ag Plus A F --AA Plus A Plus1
H H H H F=A F=A F=APlus1
'Each bit is shifted to the next more significant position.
Parameter Measurement Information
Logic Mode Test Table
Function Inputs:s1 = S2 = M = 4.5V, so = S3 = 0V
Input Other Input Other Data Inputs Output
Same Blt Output
Parameter Under Under Waveform
Teat Apply Apply Apply Apply Test
4.5V GND 4.5V GND
tPLH A; Bi None None Remaining Fi Out-of-Phase
t A and B, On
tPLH Bi A None None Jt1tl2, Fi Out-of-Phase
tPHL , n
SUM Mode Test Table
Functlon Inputs: SO = ss = 4.5V, SI = S2 = M == 0V
Input Other Input Other Data Inputs Output
Same Bit Output
Parameter Under Under Waveform
Test Apply Apply Apply Apply Test
4.5V GND 4.5V GND
tPLH A; Bi None Remaining Cn Fi In-Phase
t A and B
tPLH Bi Ai None Remaining Cn Fi In-Phase
A and B
tpLH . . Remaining -
t A. Bl None None A and B, G, P In Phase
tPLH Bi Ai None None Remaining P In-Phase
tPHL A and B, Cn
This Material Copyrighted By Its Respective Manufacturer
This Material Copyrighted By Its
Respective Manufacturer
Parameter Measurement Information (Continued)
SUM Mode Test Table
Function Inputs:So = $3 = 4.5V, St = Sit = M = 0V (Continued)
Input Other Input Other Data Inputs Output
Same Blt Output
Parameter Under Under Waveform
Test Apply Apply Appty Apply Test
4.5V GND 4.5V GND
tpLH Ai None Bi Remaining Remaining G ln-Phase
t B Ac"
tpLH Bi None Ai Remaining Remaining G ln-Phase
t B A, On
tpLH All All Any F -
t Cn None None A B or On + 4 In Phase
tPLH Ai None Bi Remaining Remaining Cn+4 Out-of-Phase
t B A, On
tPLH Bi None A Remglnlng Remaining Cn + 4 Out-of-Phase
DIFF Mode Test Table
Function Inputs: S1 = S2 = 4.5V, so = S3 = M --- 0V
Input Other Input Other Data Inputs Output
Same Bit Output
Parameter Under Under Waveform
Test Appty Apply Apply Apply Test
4.5V GND 4.5V GND
tPLH Ai None Bi Remaining Remaining Fi ln-Phase
t A ac"
tPLH Bi Ai None Remaining Remaining Fi Out-of-Phase
t A B, Cn
lpLH t . Remaining -
t A. None B. None A and B, On P In Phase
tpLH . . Remaining -
t B. A. None None A and B, On P Out-of Phase
tpLH . . Remaining -
t A. B. None None A and B, Gn G In Phase
1pm . . Remaining -
t Bi None Ai None A and B, Cn G Out-of Phase
tpLH A None Bi Remaining Remaining A = B ln-Phase
t A B, Cn
tPLH Bi Ai None Remaining Remaining A = B Out-of-Phase
t A B, Cn
tpLH All Cn + 4 -
t Cn None None A and B None or any F In Phase
tPLH Jr, Bi None None Remaining C,, + 4 Out-of-Phase
t A, B, Cn
tPLH Bi None A; None Remaining 0n + 4 In-Phase
t A, B, Cn
Logic Diagram
H8) Cn+o
(9) F0
TLfF/6560-4
Vcc == PIN 24
GND = PIN 12
This Material Copyrighted By Its Respective Manufacturer
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DM74181 N - product/dm74181n?HQS=T|-nulI-nuII-dscataIog-df-pf-null-wwe
