DM74173N ,TRI-STATE Quad RegistersFeaturesYGated enable inputs are provided for controlling the entry of TRI-STATE outputs interface ..
DM74174N , Hex D-Type Flip-Flop with ClearFeaturesY174 contains six flip-flops with single-rail outputsThese positive-edge triggered flip-flo ..
DM74174N , Hex D-Type Flip-Flop with Clear54174/DM54174/DM74174,54175/DM54175/DM74175Hex/QuadDFlip-FlopswithClearJune198954174/DM54174/DM7417 ..
DM74175N ,Hex/Quad D Flip-Flops with Clearfeatures complementary YBuffered clock and direct clear inputsoutputs from each flip-flop.YIndividu ..
DM7417M ,Hex Buffers with High Voltage Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains six independent gates each of wh ..
DM7417N ,Hex Buffers with High Voltage Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains six independent gates each of wh ..
DS1744-70 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail C ..
DS1744-70+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail C ..
DS1744-70+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION A0–A14 - Address Input CE - Chip Enable OE - Output Enable WE - Write Enable V ..
DS1744-70IND ,Y2K-Compliant, Nonvolatile Timekeeping RAMsFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail C ..
DS1744-70IND+ ,Y2K-Compliant, Nonvolatile Timekeeping RAMs DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DS1744P-70 ,Y2K-Compliant, Nonvolatile Timekeeping RAMsPIN DESCRIPTION A0–A14 - Address Input CE - Chip Enable OE - Output Enable WE - Write Enable V ..
DM74173N
TRI-STATE Quad Registers
TL/F/6556
54173/DM54173/DM74173
TRI-STATE
Quad
Registers
June 1989
54173/DM54173/DM74173
TRI-STATEÉ QuadD Registers
General Description
These four-bit registers contain D-type flip-flopswith totem-
pole TRI-STATE outputs, capableof driving highly capaci-
tiveor low-impedance loads.The high-impedance stateand
increased high-logic-level drive provide these flip-flopswith
the capabilityof drivingthebus linesina bus-organizedsys-
tem without needfor interfaceor pull-up components.
Gated enable inputsare providedfor controllingthe entryof
dataintothe flip-flops. When both data-enable inputsare
low,dataat theD inputsare loadedinto their respectiveflip-
flopsonthe next positive transitionofthe buffered clock
input. Gate output control inputsare also provided. When
bothare low,the normal logic statesofthefour outputsare
availablefor drivingthe loadsorbus lines. The outputsare
disabled independently fromthe levelofthe clockbya high
logic levelat either output control input. The outputs then
presenta high impedance andneither loadnor drivethebus
line. Detailed operationis giveninthe function table. minimizethe possibility thattwo outputswill attemptto
takea commonbusto opposite logic levels,the output con-
trol circuitryis designedsothatthe average output disable
timesare shorter thanthe average output enable times.
Features TRI-STATE outputs interface directly with systembus Gated output control linesfor enablingor disablingthe
outputs Fully independent clock elminates restrictionsfor oper-
atingin oneoftwo modes:
Parallel load nothing (hold) For applicationasbus buffer registers Typical propagation delay18ns Typical frequency30 MHz Typical power dissipation 250mW Alternate Military/Aerospace device (54173)is avail-
able. Contacta National Semiconductor Sales Office/
Distributorfor specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6556–1
OrderNumber 54173DMQB, 54173FMQB,
DM54173J, DM54173Wor DM74173N
SeeNS Package Number J16A, N16Eor W16A
Function Table
Inputs
Output
Clear Clock DataEnable Data Q G2 D X X X L X X X Q0 u HX X Q0 u XH X Q0 u LL L L u LL H H
WheneitherMorN (orboth) is(are)highthe outputis disabledtothe
high-impedance state;however, sequential operationof theflip-flopsis
not affected.ehighlevel (steady state)elowlevel (steady state)e low-to-highlevel transitione don’tcare(anyinput including transitions)ethelevelofQ beforethe indicated steady stateinput conditionswere
established
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
