DM54S189J ,4.5 V to 5.5 V, 64-bit (16 x 4) TRI-STATE RAMDM54S189/DM74S189/-....n., ...... .. _... . .- .--. .
National
Semiconductor
DM54S189/DM74S1 ..
DM54S251J ,7 V, TRI-STATE 1 of 8 line data selector/multiplexerGeneral Description
These data selectors/multiplexers contain full on-thrs bina-
u decoding to ..
DM54S287AJ ,40 ns, (256 x 4) 1024-bit TTL PROMBlock Diagram
1024B” ARRAY
32 x 32
MEMORY MATRIX
DECODER
ENABLE
GATE
Pln Names
Ad ..
DM54S287J ,60 ns, (256 x 4) 1024-bit TTL PROMFeatures
I Advanced titanium-tungsten (T i-W) fuses
I Schottky-clamped for high speed
Address ..
DM54S288AJ ,35 ns, (32 x 8) 256-bit TTL PROMBlock Diagram
M _
" man man
" 3t l 8
"EMMY MATRIX
E _,e-i-jj,li-,,el I rr,fi)-jj-i,l,)
..
DM54S288AJ ,35 ns, (32 x 8) 256-bit TTL PROMDM54SZ88/DM 748288
National
Semiconductor
DM54/ 748288 (32 x 8)
256-Bit TTL PROM
DS1685Q-5 ,3V/5V Real-Time ClocksFeatures Such as: Y2K Compliant RAM Clear Input +3V or +5V Operation Century Register ..
DS1685S-3 ,3V/5V Real-Time Clocksfeatures including a silicon serial number, power-on/off control circuitry, 242 bytes of user NV SR ..
DS1685S-5 ,3V/5V Real-Time Clocksfeatures described above. An external crystal and battery are the only components required to maint ..
DS1685S-5+ ,3V/5V Real-Time ClockFEATURES PIN ASSIGNMENT (Top View)Incorporates industry-standard DS1287 PC clockplus enhanced
DS1685SN-5 ,3V/5V Real-Time ClocksFEATURES Incorporates Industry-Standard DS1287 PC Clock plus Enhanced
DS1685SN-5+ ,3V/5V Real-Time Clockfeatures:PWR 1 24 VCC Y2K-compliant2X1 23 SQW +3 or +5V operationX23 22 VBAUX 64-bit silicon ser ..
DM54S189J-DM74S189J-DM74S189N
4.5 V to 5.5 V, high speed 64-bit TRI-STATE RAM
DM54S189/DM74S189/DM54S189A/DM74S189A
National
_ Semiconductor
DM54S189/DM74S189 64-Bit (16 x 4) TRl-STATE® RAM
DM54S189A/DM74S189A High Speed 64-Bit
TRi-STATE RAM
General Description
These 64-bit active-element memories are monolithic
Schottky-clamped transistor-transistor logic (TTL) arrays or-
ganized as 16 words of 4 bits each. They are fully decoded
and feature a chip-enable input to simplify decoding re-
quired to achieve the desired system organization. The
memories feature PNP input transistors that reduce the low
level input current requirement to a maximum of -0.25 mA,
only one-eighth that of a DM74S standard load factor. The
chip-enable circuitry is implemented with minimal delay
times to compensate for added system decoding.
The TRI-STATE output combines the convenience of an
open-collector with the speed of a totem-pole output; it can
be bus-connected to other similar outputs; yet it retains the
fast rise time characteristics of the TTL totem-pole output.
Systems utilizing data bus lines with a defined pulI-up im-
pedance can employ the open-collector DM74S289.
Write Cycle: The complement of the information at the data
input is written into the selected location when both the
chip-enable input and the read/write input are low. While
the read/write input is low, the outputs are in the high-im-
pedance state. When a number of the DM74S189 outputs
are bus connected, this high-impedance state will neither
load nor drive the bus line, but it will allow the bus line to be
driven by another active output or a passive pull-up if de-
sired.
Read Cycle: The stored information (complement of infor-
mation applied at the data inputs during the write cycle) is
available at the outputs when the read/write input is high
and the chip-enable is low. When the chip-enable is high,
the outputs will be in the high-impedance state.
The fast access time of the DM74S1 89A makes it particular-
ly attractive for implementing high-performance memory
functions requiring access times less than 25 ns. The high
capacitive drive capability of the outputs permits expansion
without additional output buffering. The unique functional
capability of the DM748189A outputs being at a high-irnped-
ance during writing, combined with the data inputs being
inhibited during reading, means that both data inputs and
outputs can be connected to the data lines of a bus-orga-
nized system without the need for interface circuits.
Features
II Schottky-clamped for high speed applications (S189A)
Access from chip-enable input 17 ns max
Access from address inputs 25 ns max
I: TRI-STATE outputs drive bus-organized systems and/or
high capacitive loads (S189, S189A)
ll DM74S289 are functionally equivalent and have open-
collector outputs
" DM54SXXX is guaranteed for operation over the full
military temperature range of -55''C to +125°C
n Compatible with most ITL circuits
u Chip-enable input simplifies system decoding
Connection Diagram
Dual-ln-Llne Package
SELECT INPUTS DATA
[NWT 0 UYPUT
INPUT O UTPUT
Vet: "
In 15 u 13 " I u in I '
t t 3 I 5 6 , I
SELECT CHIP READ]
INPUT! [NAILS WRITE
DATA OUTPUT DATA OUTIUT 6ND
MP0t TI INPUT "
TL/D/9232-1
Top View
Truth Table
Inputs
Function Chlp- Read/ Output
Enable Write
grpfj:;:t of Data) L L High-lmpedance
Read L H Stored Data
Inhibit H X High-lmpedance
H = High Level, L = Low Level, X = Don't Care
Order Number DM545189J, DM54S189AJ,
DM74S189J. DM74S189AJ,
DM74S189N or DM74S189AN
See NS Package Number J16A or N16E
Absolute Maximum Ratings (Note1)
Operating Conditions
If Mllltary/Aerospace speclfled devlces are required, Min Max Units
please contact the National Semiconductor Sales Supply Voltage (Vcc)
Offlce/Dlstrlbutors for availability and specifications. DM54S189 4.5 5.5 V
Supply Voltage, VCC 7.0V DM74S189 4.75 5.25 V
Input Voltage 5.5V Temperasture (TA)
DM54 189 -55 + 125 "C
Output Voltage 5.5V DM74S189 o + 70 'C
Storage Temperature Range -65"C to + 150''C
Lead Temperature (Soldering, 10 sec.) + 300°C
DM54S189, DM74S189 Electrical Characteristics
over recommended operating free-air temperature range unless otherwise noted (Notes 2 and 3)
Symbol Parameter Conditions Min Typ Max Unlts
Ihre High Level Input Voltage 2 V
VIL Low Level Input Voltage 0.8 V
VOH High LevelOutput Vcc = Min 'OH = -2.0 mA, 2 4 3 4 V
Voltage DM54S189 . .
IOH = -6.5 mA,
DM74S189 2,4 3.2 V
ICEX High Level Output Current Vcc = Min VOH = 2.4V 40
0 en Collector Onl “A
p y VOH = 5.5V 100
VOL Low Level Output Vcc = Min, DM54S189 0.5 V
Voltage kx = 16 mA DM74S189 0.45 v
IIH High Level Input Current Vcc = Max, V. = 2.7V 25 'p.A
ll High Level InputCurrent VCC = Max, VI = 5.5V
. 1.0 mA
at Maximum Voltage
'lL Low Level lnputCurrent Vcc = Max, VI = 0.45V -250 p.A
los Short Circuit Output Vcc = Max, DM54S189, _ 30 _ 100 m A
Current (Note 4) V0 = 0V DM74S189
Icc Supply Current (Note 5) Vcc = Max 75 110 mA
v.0 Input Clamp Voltage Vcc = Min, l; = - 18 mA --1.2 V
IOZH TRI-STATE Output Current, VCC = Max, DM54S189, 50 A
High Level Voltage Applied V0 = 2.4V DM74S189 P
IOZL TRI-STATE Output Current, Vcc = Max, DM54S189, - 50 A
Low Level Voltage Applied Vo = 0.45v DM74S189 "
CIN InputCapacitance Vcc = 5V, VIN = 2V, 4 0 F
TA = 25°C, 1 MHz . p
Co OutputCapacitancts Vcc = 5V, V0 = 2V,
TA = 25''C, 1 MHz, 6.0 pF
Output "Off"
V68lSflWO/VGSLSVSWO/GSlSflWO/GBLSVSWG
DM54S189/DM74S189/DM54S189A/DM74S189A
DM74S189 Switching Characteristics
over recommended operating ranges of TA and Vcc unless otherwise noted
DM54S189 DM74S189
Symbol Parameter Cortdltltttttt Min Typ Max Min Typ Max Units
(Note 2) (Note 2)
tAA Access Times from Address CL = 30 pF, 25 50 25 35 ns
. R --- 2800
tczH Output Enable Time to L .
High Level Access Times from (Figure 4) 12 25 12 17 ns
. ChIP-Enable
tCZL Output Enable Time to 1 2 25 1 2 17 ns
Low Level
tWZH Output Enable Time to
High Level Sense Recovery Times 13 35 13 25 ns
. from Read/Write
tWZL Output Enable Time to 1 3 35 13 25 ns
Low Level
tCHz Output Disable Time th. = 5 pF,
from High Level Disable Times from RL = 2800 12 25 12 17 ns
ttag Output Disable Time CNP-Enable (Figure 4)
1 2 25 1 2 1 7 ns
from Low Level
tWHz Output Disable Time
from High Level Disable Times from 15 35 15 25 ns
tWLz Output Disable Time Read/Write
15 35 15 25 ns
from Low Level
twp Width of Write Enable Pulse (Read/Write Low) 25 25 ns
tAsw Set-Up Time (Figure 1) Address to Read/Write 0 0 ns
tpsw Data to Read/Write 25 25 ns
ttsw Chip-Enable to
Read/Write o o ns
tAHw Hold Time (Figure " Address from Read/Write ns
tDHw Data from Read/Write ns
tCHw Chip-Enable from
Read/Write o 0 ns
Absolute Maximum Ratings (Note1)
Operating Conditions
If Mllltary/Aerospace ttpetrified devices are required, Min Max Units
please contact the National Stttttlttorttiutttor Sales Supply Voltage (Vcc)
ottltNtfDltttrittutttrtt for availability and specifications. DM54S189(A) 4.5 5.5 V
Supply Voltage, Vcc 7.0V DM74S189(A) 4.75 5.25 V
InputVoltaiN 5.5V '12"s"4agq'JJf 55 +125 ''C
Output Voltage 5.5V DM74S189(A) 0 +70 °c
Storage Temperature Range --65'C to + 150°C
Lead Temperature (Soldering, 10 sec) + 300°C
DM54S189A, DM74S189A Electrical Characteristics
over recommended operating free-air temperature range unless otherwise noted (Notes 2 and 3)
Symbol Parameter Condltlons Mln Typ Max Units
w, High Level Input Voltage 2 V
" Low Level Input Voltage 0.8 V
VOH High LevelOutput Vcc = Min IOH --- -2.0 mA, 2 4 3 4 V
Voltage DM54S189A . .
IOH = -6.5 mA,
DM74S189A 2.4 3.2 V
VOL Low Level Output Vcc = Min lot. = 16 mA 0.45 V
Voltage kx = 20 mA 0.5
IIH High Level lnputCurrent VCC = Max, VI = 2.4V 10 p.A
I. High Level InputCurrent Vcc = Max, V. = 5.5V
1.0 mA
at Maximum Voltage
ll. Low Level InputCurrent Vcc = Max,V. = th40V -250 . MA
los Short CircuitOutput Vcc == Max, Vo == 0V _ -
Current (Note 4) 20 90 mA
'00 Supply Current (Note 5) Vcc == Max 75 100 mA
Vic InputClamp Voltage Vcc --= Min, 11 = --18 mA -I.2 V
IOZH TRl-STATE OutputCurrant. Vcc = Max, Vo = 2.4V 40 A
High Level Voltage Applied M
km. TRI-STATE Output Current, Vcc = Max, Vo = 0.4V -40 A
Low Level Voltage Applied P’
Cm Input Capacitance Vcc = 5V, I/tN = 2V, 4 0 F
TA = 25''C, 1 MHz . p
Co OutputCapacitance Vcc = 5V, V0 = 2V,
TA = 25''C, 1 MHz, 6.0 pF
Output "Off"
V68lSt’lWG/VGBlSVSWO/GBLSHWG/GGlSVSWG
DM54S189/DM74S189/DM54S189A/DM74S189A
DM54S189A, DM74S189A Switching Characteristics
over recommended operating ranges of TA and Vcc unless otherwise noted
DM548189A DM74S189A
Symbol Parameter Conditions Min Typ Max Min Typ Max Unlts
(Note 2) (Note 2)
tAA Access Time from Address CL = 30 pF, 20 30 20 25 ns
tCZH Output Enable Time to RL , 280n 1 1 25 1 1 17 ns
High Level Access Times from (Figure 4)
. Chip-Enable
tCZL Output Enable Time to 11 25 11 17 ns
Low Level
tWZH Output Enable Time to
High Level Sense Recovery Times 13 35 13 25 ns
. from Read/Write
tWZL Output Enable Time to 1 3 35 1 3 25 ns
Low Level
tCHZ Output Disable Time CL = 5 pF,
from High Level Disable Times from RL = 280n 12 25 12 17 ns
tCLz Output Disable Time Chip-Enable (Figure 4)
12 25 12 17 ns
from Low Level
tWHz Output Disable Time
from High Level Disable Times from 15 35 15 25 ns
. . Read/Write
tWLz Output Disable Time 1 5 35 1 5 25 ns
from Low Level
twp Width of Write Enable Pulse (Read/Write Low) 25 20 ns
lAsw Set-Up Time (Figure 1) Address to Read/Write 0 0 ns
tDSW Data to Read/Write 25 20 ns
tcsw Chip-Enable to
Read/Write 0 0 ns
tAHw Hold Time (Figure I) Address from Read/Write 0 ns
tDHw Data from Read/Write ns
tCHw Chip-Enable from
Read/Write 0 o ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified min/max limits apply across the -55''C to + 125'C temperature range for the DM54$189(A) and across the tPC to + 7tt'C
range for the DM74S189(A). All typicals are given for Vcc = 5.0V and TA --- 25'C,
Note & All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note s.. ICC is measured with all inputs grounded; and the outputs open.
DM54S189(A), DM74S189(A) Switching Time Waveforms
Enable and Disable Time from Chlp-Enable
cmr EIAILE 'l'""'""-""""', tGT""'""
INPUT (MUTE 3)
---tc" "r-r-.- tec
WAVEFBRMI M,W
(NOTE I) T Lil-,,-
_ km ---i
mvsromz tlor,
mom) 7157
Access Tlme from Address Inputs
TL/D/9232-2
ADDRESS " ''""--s
murs I t.5tt
mom) mt--." N----.--.
taa Bu
OUTPUT t.W 1.5V
TL/D/9232-3
Write Cycle
" - - - - - - - - -
ADDRESS "
nmns Mtt
mt - '
tht - - -
cmrsuu:
nunlwm: 's
mrut te'' ' /
art.Stt Hula} l MW "l,,
WAVEFDRMI .
(nor: 1) /K.5v
Ito. i SL.?
- tmeg - I -.--- ttear,
wmrom l v0.
Ji1ds'i'li k--)'-'-'' MN
(NOTE tl tt.Mt
TL/D/9232-4
FIGURE 1
Not. 1: Waveform 1 is tor the output with internal conditions such that the output is low except when disabled. Waveform 2 is for the output with internal conditions
such that the output is high except when disabled.
Note 2: When measuring delay times from address inputs, the ehithertaNe input is low and the read/wn'te Input is high.
Note 3: When measuring delay times from chip-enable input, the address inputs are steady-state and the read/wn'te input is high.
Note W. Input waveforms are supplied by pulse generators having the following characteristics: k 5 2.5 ns, t. s 2.5 ns, PRR s 1 MHz and 2our .. = son.
V68LSPLWG/VGBLSVEWG/GBI-SMWG/GGI-SVSWCI
DM54S189/DM74S189/DM54S189A/DM74S189A
Block Diagram
ADDRESS
INPUTS 14
ADDRESS
BUFFERS
1 OF tt
DECODERS
G&BITMEMDEV
MATRIX
ORGANIZED
16 It 4
AC Test Circuits
CL includes probe and iig capacitance.
All diodes are IN3084.
cm? ENABLE (ti) ---<,
WRITE AND SENSE
3 AMPLIFIER comaoL
REA01WRiTE (n/W)
a,s......d
o M til
ATAINPUTS us
5 7 s lt
yt v2 " "
ourru1s
TL/D/9232-5
FIGURE3
DM54S189(A)/DM748189(A)
FIGURE 4
TL/D/9232-6
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
DM54S189AJ - product/dm54s189a]?HQS=TI-null-nulI-dscatalog-df-pf—nuII-wwe
DM74S189N - product/dm74s189n?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuIl-wwe
DM74S189J - product/dm74s189]?HQS=T|—nu|I-nulI-dscatalog-df—pf—nuII-wwe
DM54S189J - product/dm54s189]?HQS=T|-nu|I-nulI—dscatalog-df—pf—nuII-wwe
DM74S189AN - product/dm74s189an?HQS=T|-nu|l-nu|l-dscatalog-df-pf—nuII-wwe
DM74S189AJ - productldm74s189a]?HQS=T|—nul|-null-dscatalog-df—pf—nuII-wwe
