DM54LS471J ,70 ns, (256 x 8) 2048-bit TTL PROMElectrical Characteristics (Note1)
Symbol Parameter Conditions DM54LS471 DM74LS471 Units
Min Typ ..
DM54LS471J ,70 ns, (256 x 8) 2048-bit TTL PROMDM54LS471/DM74LS471
National
Semiconductor
DM54/74LS471
(256 x 8) 2048-Bit TTL PROM
DM54LS471J ,70 ns, (256 x 8) 2048-bit TTL PROMGeneral Description
These Schottky memories are organized in the popular 256
words by 8 bits co ..
DM54LS74AJ ,Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary OutputsFeaturesof the rising edge of the clock. The data on the D input mayYAlternate military/aerospace d ..
DM54LS86J ,Quad 2-Input Exclusive-OR GatesDM54LS86/DM74LS86Quad2-InputExclusive-ORGatesJune1989DM54LS86/DM74LS86Quad2-InputExclusive-ORGatesG ..
DM54LS86J ,Quad 2-Input Exclusive-OR GatesDM54LS86/DM74LS86Quad2-InputExclusive-ORGatesJune1989DM54LS86/DM74LS86Quad2-InputExclusive-ORGatesG ..
DS1672S/3 ,Low Voltage Serial Time Keeping ChipPRELIMINARYDS1672Low Voltage Serial Timekeeping ChipPIN ASSIGNMENT
DS1672S-3 ,Low Voltage Serial Time Keeping ChipPIN DESCRIPTIONV V - Power Supply InputsCC, BACKUPORDERING INFORMATIONGND - GroundDS1672X-XX1, X2 - ..
DS1672S-33+ ,I²C 32-Bit Binary Counter RTCFEATURES 32-Bit Counter The DS1672 incorporates a 32-bit counter and 2power-monitoring functions. ..
DS1672S-33+T&R ,I²C 32-Bit Binary Counter RTC19-6032; Rev 9/11 DS1672 2 I C 32-Bit Binary Counter RTC
DS1672U-33 ,Low Voltage Serial Timekeeping ChipFEATURES 32-bit counterX1 1 8 VCC 2-wire serial interface Automatic power-fail detect and switch ..
DS1672U-33 ,Low Voltage Serial Timekeeping Chipblock diagram in Figure 1 shows the main elements of the DS1672. As shown, communications toand fr ..
DM54LS471J-DM74LS471J-DM74LS471N
70 ns, (256 x 8) 2048-bit TTL PROM
DM54LS471/DM74LS471
National
Semiconductor
DM54/74LS471
(256 x 8) 2048-Bit TTL PROM
General Description
These Schottky memories are organized in the popular 256
words by 8 bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled, the outputs represent the contents of the selected
word. When disabled, the 8 outputs go to the "OFF" or high
impedance state.
PROMs are shipped from the factory with laws in all loca-
tions. A high may be programmed into any selected location
by following the programming instructions.
Features
" Advanced titanium-tungsten (T MN) fuses
II Schottky-clamped for high speed
Address access down to-tio ns max
Enable atrtxtss-30 ns max
Enable recovery-GO ns max
I: PNP inputs for reduced input loading
" All DC and AC parameters guaranteed over tempera-
a Low voltage TRl-SAFETM programming
" TRI-STATE8 outputs
Block Diagram
ttwr8tr ARRAY
3t x 64
A5 MEMORY MATRIX
DECUDEH
GATE m 08 05 04 03 02 01 00
TL/D/NM-t
Pln Names
Ao-A7 Addresses
ET-E Output Enables
GND Ground
00-07 Outputs
Vcc Power Supply
Connection Diagrams
Dual-ln-Llne Package
wcnumuugun-
20 -vcc
18 -A6
17 -A5
16 .-trt
15 -trt
14 -07
13 -06
12 -05
11 -04
TL/D/9190-2
Order Number DM54/74LS471J or DM74LS471N
See NS Package Number J20A or N20A
Ordering Information
Plastic Leaded Chip Carrier (PLCC)
Q : 2 >8:
I I I I I
3 2 1 2019
113-4 18r-h6
A4-5 17 L115
Co-rt; 16--tF2
01-7 Iti-6i
tl2--8 14-07
9 IO 11 1213
I l I l l
70 Ch V In u:
c, = 0 O O
TopView
Order Number DM74LS471V
See NS Package Number V20A
Commercial Temp Range (0°C to + 70°C)
Parameter/Order Number Max Access Time (ns)
DM74LS471 N 60
DM74LS471 J 60
DM74LS471 V 60
Military Temp Range t
-55''C to + 125''C)
Parameter/Order Number
Max Access Time (ns)
DM54LS471 J
TL/D/9190~3
l-AVS'IVLWCI/ HVS'WSWCI
DM54LS471/DM74LS471
Absolute Maximum Ratings (Note1)
Operating Conditions
" Mllltary/Aerospace specified devices are required, Min Max Units
please contact the National Semiconductor Sales Supply Voltage (V00)
Oflice/Dlstributors for availability and specifications. Military 4.50 5.50 V
Supply Voltage (Note 2) - 0.5V to + 7.0V CQWWemia' 4.75 5.25 V
Input Voltage (Note 2) - 1 .2V to + 5.5V A"ibiltlt Temperature (TA) 55 + 125 C
Output Voltage (Note 2) - 0.5V to ' 5.5V céhgercial 0 + 70 "C
Storage Temperature - 65°C to +150°C Logical "o" Input Voltage 0 0.8 V
Lead Temp. (Soldering, 10 seconds) 300°C Logical "I " Input Voltage 2.0 5.5 V
ESD to be determined
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be permanently damaged. They do not mean that the device may
be operated at these values.
Note 2: These limits do not apply during programming ratings, refer to the
programming instructions,
DC Electrical Characteristics (Note1)
Symbol Parameter Conditions DM54LS471 DMr4LS471 Unlts
Min Typ Max Min Typ Max
IIL Input Load Current Vcc = Max, VlN = 0.45V -80 -250 - 80 -250 p.A
IIH Input Leakage Current Vcc = Max, VlN = 2.7V 25 25 HA
Vcc = Max, VIN = 5.5V 1.0 1.0 mA
VOL Low Level Output Voltage VCC = Min, IOL = 16 mA 0.35 0.50 0.35 0.45 V
" Low Level Input Voltage 0.80 0.80 V
ViH High Level Input Voltage 2.0 2.0 V
Vc Input Clamp Voltage VCC = Min, IIN = -18 mA - 0.8 - 1.2 --0.8 - 1.2 V
CI Input Capacitance Vcc = 5.0V, VIN = 2.0V
TA = 25''C, 1 MHz 4.0 4.0 d pF
Co Output Capacitance Vcc = 5.OV, Vo = 2.0V 6 0 6 0 F
TA = 25''C, 1 MHz, Outputs Off . . p
'00 Power Supply Current VCC = Max, Inputs Grounded 75 100 75 100 m A
All Outputs Open
log Short Circuit V0 = 0V, Vcc = Max _ - _ _
Output Current (Note 2) 20 70 20 70 mA
Ioz Output Leakage VCC = Max, V0 = 0.45V to 2.4V +50 + 50 p.A
(TRI-STATE) Chip Disabled - 50 - 50 " A
VOH Output Voltage High IOH = -2.0 mA 2.4 3.2 V
IOH = - 6.5 mA 2.4 3.2 V
Note I.. These limits apply over the entire operating range unless stated otherwise. All typical values are for VCC = 5.0V and TA = 25'C.
Note 2: During los measurement. only one output at a time should be grounded. Permanent damage may otherwise result.
AC Electrical Characteristics with Standard Load and Operating Conditions
Symbol JEDEC Symbol Parameter DM54LS471 DM74LS47t Units
Min Typ Max Min Typ Max
TAA TAVQV Address Access Time 45 70 40 60 ns
TEA TEVQV Enable Access Time 15 35 15 30 ns
TER TEXQX Enable Recovery Time 15 35 15 30 ns
TZX TEVQX Output Enable Time 15 35 15 30 ns
TXZ TEXQZ Output Disable Time 15 35 15 30 ns
Functional Description
TESTABILITY
The Schottky PROM die includes extra rows and columns of
tusable links for testing the programmabiiity of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the program-
ming tests in the final product. A ROM pattern is also per-
manently fixed in the additional circuitry and coded to pro-
vide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and column-select circuits and functionality of input and en-
able gates. All test circuits are available at both water and
assembled device levels to allow 100% functional and para-
metric testing at every stage of the test flow.
RELIABILITY
As with all National products, the Ti-W PROMs are subject-
ed to an on-going reliability evaluation by the Reliability As-
surance Department. These evaluations employ accelerat-
ed life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling. and ther-
mal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configura-
tions is excellent.
TlTANlUM-TUNGSTEN FUSES
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to pro-
gram efficiently with only 10.5V applied. The high perform-
ance and reliability of these PROMs are the result of fabrica-
tion by a Schottky bipolar process, of which the titanium-
tungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasites The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire oper-
ating ranges of Vcc and temperature.
llVS‘lVLWG/llt’S'WSWG
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
DM74LS471V - product/dm74ls471v?HQS=TI-null-nulI-dscatalog-df-pf—nuII-wwe
DM54LS471J - product/dm54ls471j?HQS=T|-nulI-nuII-dscatalog-df—pf—nuII-wwe
DM74LS471J - product/dm74ls471j?HQS=T|-nulI-nuII-dscatalog-df—pf—nuII-wwe
DM74LS471 N - product/dm74ls471n?HQS=TI-null-nu|I-dscataIog-df—pf—nuII-wwe
