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DM54LS259J/883
8-Bit Serial In to Parallel Out Addressable Latches
TL/F/6418
DM54LS259/DM74LS259
8-Bit
Addressable
Latches
May 1992
DM54LS259/DM74LS259 8-Bit Addressable Latches
General Description
These 8-bit addressable latchesare designedfor general
purpose storage applicationsin digital systems. Specific
uses include working registers, serial-holding registers,and
active-high decodersor demultiplexers. Theyare multifunc-
tional devices capableof storing single-line datain eight
addressable latches,and beinga 1-of-8 decoderor demulti-
plexer with active-high outputs.
Four distinct modesof operationare selectableby control-
lingthe clearand enable inputsas enumeratedinthe func-
tion table.Inthe addressable-latch mode, dataatthe data- terminalis written intothe addressed latch. Thead-
dressed latchwill followthe data input withall unaddressed
latches remainingin their previous states.Inthe memory
mode,all latches remainin their previous states andare
unaffectedbythe dataor address inputs.To eliminatethe
possibilityof entering erroneous datainthe latches,theen-
able shouldbe held high (inactive) whilethe address lines
are changing.In the 1-of-8 decodingor demultiplexing
mode,the addressed outputwill followthe leveloftheD
input withall other outputs low.Inthe clear mode,allout-
putsarelowand unaffected bythe address anddata inputs.
Features 8-Bit parallel-out storage register performs serial-to-par-
allel conversion with storage Asynchronous parallel clear Active high decoder Enable/disable input simplifies expansion Direct replacementfor Fairchild 9334 Expandablefor N-bit applications Four distinct functional modes Typical propagation delay times:
Enable-to-output18ns
Data-to-output16ns
Address-to-output21ns
Clear-to-output17ns Fan-out
IOL (sink current)
54LS2594mA
74LS2598mA
IOH (source current) b0.4mA TypicalICC22mA
Connection Diagram
Dual-In-Line Package
TL/F/6418–1
OrderNumberDM54LS259E, DM54LS259J,
DM54LS259W, DM74LS259M,
DM74LS259WMor DM74LS259N
SeeNS Package Number E20A, J16A,
M16A, M16B, N16Eor W16A
Function Table
Inputs Outputof Each
Addressed Other Function
ClearE Latch Output D Qi0 Addressable Latch Qi0 Qi0 Memory L D L 8-Line Demultiplexer H L L Clear
Latch Selection Table
SelectInputs Latch A Addressed
LLL 0 H 1
LHL 2 H 3 L 4
HLH 5 L 6
HHH 7eHigh Level,Le LowLevelethe Levelof theDataInput
Qi0ethe LevelofQi(ie0,1,...7,as Appropriate) beforethe Indicated
Steady-StateInput Conditions Were Established.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
