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DM54LS279J ,Quad S-R LatchesFeaturesstored in the latch and appear on the corresponding Q out-YAlternate military/aerospace dev ..
DM54LS283J ,4-Bit Binary Adders with Fast CarryFeaturesYFull-carry look-ahead across the four bitsThese full adders perform the addition of two 4- ..
DM54LS32J ,Quad 2-Input OR Gates54LS32/DM54LS32/DM74LS32Quad2-InputORGatesMay198954LS32/DM54LS32/DM74LS32Quad2-InputORGatesGeneralD ..
DM54LS365AJ ,Hex TRI-STATE BuffersFeatureslines without external resistors. When disabled, both theYAlternate Military/Aerospace devi ..
DS1669 ,Dallastat Electronic Digital RheostatPIN DESCRIPTION DS1669 R - High Terminal of Potentiometer H R - Wiper Terminal of Potentiometer ..
DS1669-010 , Dallastat Electronic Digital Rheostat
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DS1669-10 ,Electronic digital rheostat, ~ 10 k.Applications include volume, tone, contrast,brightness, and dimmer control8-Pin SOIC (208-mil) Ava ..
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DM54LS251J
TRI-STATE Data Selectors/Multiplexers
TL/F/6415
DM54LS251/DM74LS251
TRI-STATE
Data
Selectors/Multiplexers
June 1989
DM54LS251/DM74LS251
TRI-STATEÉ Data Selectors/Multiplexers
General Description
These data selectors/multiplexers containfull on-chip bina- decodingto select one-of-eight data sources, andfeature strobe-controlled TRI-STATE output. The strobe mustbealow logic level toenablethesedevices.The TRI-STATE
outputs permit direct connectiontoa common bus. When
the strobe inputis high, both outputsareina high-imped-
ance statein which boththe upperand lower transistorsof
each totem-poleoutputare off,and theoutput neither drives
nor loadsthebus significantly. Whenthe strobeis low,the
outputsare activatedand operateas standard TTL totem-
pole outputs. minimizethe possibilitythattwo outputswill attemptto
takea commonbusto opposite logic levels,the output con-
trol circuitryis designedsothatthe average output disable
timeis shorter thanthe average output enable time.
Features TRI-STATE versionof LS151 Interface directly with systembus Perform parallel-to-serial conversion Permit multiplexing from N-linestooneline Complementary outputs providetrueand inverted data Maximum numberof common outputs
54LS49
74LS 129 Typical propagation delay time(DtoY)
54LS17ns
74LS17ns Typical power dissipation
54LS35 mW
74LS35 mW
Connection Diagram
Dual-In-Line Package
TL/F/6415–1
OrderNumberDM54LS251J, DM54LS251W,
DM74LS251Mor DM74LS251N
See NSPackage Number J16A, M16A, N16Eor W16A
Function Table
Inputs Outputs
Select Strobe YW
CBA S
XXX H Z Z L L L D0 D0 L H L D1 D1 H L L D2 D2 H H L D3 D3 L L L D4 D4 L H L D5 D5 H L L D6 D6 H H L D7 D7eHigh Logic Level,Le LowLogicLevel,e Don’t Care,ZeHigh Impedance(Off)
D0, D1...D7eThelevelofthe respectiveDinput
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
