DM74LS190N ,Synchronous 4-Bit Up/Down Counters with Mode ControlDM54LS190/DM74LS190,DM54LS191/DM74LS191Synchronous4-BitUp/DownCounterswithModeControlMay1989DM54LS1 ..
DM74LS191N ,Synchronous 4-Bit Up/Down Counters with Mode ControlGeneral Descriptioncading function: ripple clock and maximum/minimum count.The DM74LS191 circuit is ..
DM74LS192N ,54LS192/DM74LS192 Up/Down Decade Counter with Separate Up/Down Clocks54LS192/DM74LS192Up/DownDecadeCounterwithSeparateUp/DownClocksMay199254LS192/DM74LS192Up/DownDecade ..
DM74LS192N ,54LS192/DM74LS192 Up/Down Decade Counter with Separate Up/Down Clocks54LS192/DM74LS192Up/DownDecadeCounterwithSeparateUp/DownClocksMay199254LS192/DM74LS192Up/DownDecade ..
DM74LS193MX , Synchronous 4-Bit Up/Down Binary Counter with Dual ClockGeneral Descriptioninputs are buffered to lower the drive requirements of clockThe DM74LS193 circui ..
DM74LS193N ,Synchronous 4-Bit Binary Counter with Dual ClockFeatures
I Fully independent clear input
I Synchronous operation
I Cascading circuitry pro ..
DS2186+ ,Transmit Line InterfacePIN DESCRIPTION Table 1PIN SYMBOL TYPE DESCRIPTION1 TAIS I Transmit Alarm Indication Signal. When ..
DS2186S ,Transmit Line Interfaceapplications.DD4 LEN0 I Length Select 0, 1 and 2. State determines output T1 waveform5 LEN1 shape ..
DS2186S ,Transmit Line InterfaceBLOCK DIAGRAM Figure 1VSSLNEGLPOSTTIPLCLKINPUT ZERO CODELINEWAVESHAPPINGDATA SUPPRESSIONDRIVERSTNEG ..
DS2186S+ ,Transmit Line Interfaceapplications are supported. Appropriate CCITT recom-communications networks. The device is compatib ..
DS2187 ,Receive Line Interfaceapplications such as AVSS 10 11 DVSSterminal equipment to DSX-1 20-Pin S ..
DS2187+ ,Receive Line Interfaceapplications utilize a 18.528 MHz clock divided by either11, 12, or 13 to match the phase of the in ..
DM54LS191J-DM74LS190N
Synchronous 4-Bit Up/Down Counters with Mode Control
TL/F/6405
DM54LS190/DM74LS190,
DM54LS191/DM74LS191
Synchronous
4-Bit
Up/Down
Counters
with
Mode
Control
May 1989
DM54LS190/DM74LS190, DM54LS191/DM74LS191
Synchronous 4-Bit Up/Down Counters with Mode Control
General Description
These circuitsare synchronous, reversible, up/down coun-
ters.The LS191isa 4-bit binary counterandthe LS190isa
BCD counter. Synchronous operationis providedby having
all flip-flops clocked simultaneously,so thatthe outputs
change simultaneously whenso instructedbythe steering
logic. This modeof operation eliminatesthe output counting
spikes normally associatedwith asynchronous (ripple clock)
counters.
The outputsofthefour master-slave flip-flopsare triggereda low-to-high level transitionofthe clock input,ifthe
enable inputislow.A highatthe enable input inhibits count-
ing. Level changesat eitherthe enable inputorthe down/ input shouldbe made only whenthe clock inputis high.
The directionofthe countis determinedbythe levelofthe
down/up input. Whenlow,the counter countsupand when
high,it counts down.
These countersare fully programmable;thatis,the outputs
maybe presetto either levelby placingalowonthe load
inputand enteringthe desired dataatthe data inputs.The
outputwill change independentofthe levelofthe clockin-
put. This feature allowsthe counterstobe usedas modulo- dividersby simply modifyingthe count length withthe
preset inputs.
The clock, down/up,and load inputsare bufferedto lower
the drive requirement; which significantly reducesthe num-
berof clock drivers, etc., requiredfor long parallel words.
Two outputs have been made availableto performthe cas-
cading function: ripple clockand maximum/minimum count.
The latter output producesa high-level output pulse witha
duration approximately equaltoone complete cycleofthe
clock whenthe counter overflowsor underflows.The ripple
clock output producesa low-level output pulse equalin
widthtothe low-level portionofthe clock input whenan
overflowor underflowcondition exists.The counterscanbe
easily cascadedby feedingthe ripple clock outputtothe
enable inputofthe succeeding counterif parallel clockingis
used,ortothe clock inputif parallel enablingis used. The
maximum/minimum count output canbe usedto accom-
plish look-aheadfor high-speed operation.
Features Counts 8-4-2-1 BCDor binary Single down/up count controlline Count enable control input Ripple clock outputfor cascading Asynchronously presettable with load control Parallel outputs Cascadablefor n-bit applications Average propagation delay20ns Typical clock frequency25 MHz Typical power dissipation 100mW
Connection Diagram
Dual-In-Line-Package
TL/F/6405-1
Order Number DM54LS190J, DM54LS191J, DM54LS190W,
DM54LS191W,DM74LS190M, DM74LS191M, DM74LS190N,or DM74LS191N
SeeNS Package Number
J16A,M16A, N16Aor W16A
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
