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DM54LS169AJ
Synchronous 4-Bit Up/Down Binary Counter
TL/F/6401
54LS169/DM54LS169A/DM74LS169A
Synchronous
4-Bit
Up/Down
Binary
Counter
June 1989
54LS169/DM54LS169A/DM74LS169A
Synchronous 4-Bit Up/Down Binary Counter
General Description
This synchronous presettable counter featuresan internal
carry look-aheadfor cascadingin high-speed countingap-
plications. Synchronous operationis providedby havingall
flip-flops clocked simultaneously,so thatthe outputsall
changeatthe same time whenso instructedbythe count-
enable inputsand internal gating. This modeof operation
helps eliminatethe output counting spikesthatare normally
associated with asynchronous (ripple clock) counters.A
buffered clock input triggersthefour master-slave flip-flopsthe rising edgeofthe clock waveform.
This counteris fully programmable;thatis,the outputs may
eachbe preset either highor low. The load input circuitry
allows loading withthe carry-enable outputof cascaded
counters.As loadingis synchronous, settingupalow levelthe load input disablesthe counterand causestheout-
putsto agreewiththe data inputs afterthe next clock pulse.
The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional gating.
Both count-enable inputs(PandT) mustbelowto count.
The directionofthe countis determinedbythe levelofthe
up/down input. Whenthe inputis high,the counter counts
up; when low,it counts down. InputTisfed forwardtoen-
ablethe carry outputs. The carry output thus enabledwill
producea low-level output pulse witha duration approxi-
mately equaltothe high portionoftheQA output when
countingup,and approximately equaltothelow portionof
theQA output when counting down. This low-level overflow
carry pulsecanbe usedto enable successively cascaded
stages. Transitionsatthe enablePorT inputsare allowed
regardlessofthe levelofthe clock input. Allinputs arediode
clampedto minimize transmission-line effects, thereby sim-
plifying system design.
This counter featuresa fully independent clock circuit.
Changesat control inputs (enableP, enableT, load, up/
down), which modifythe operating mode, haveno effect
until clocking occurs.The functionofthe counter (whether
enabled, disabled, loading,or counting)willbe dictated
solelybythe conditions meetingthe stable setupand hold
times.
Features Fully synchronous operation for counting and
programming. Internal look-aheadforfast counting. Carry outputfor n-bit cascading. Fully independent clock circuit Alternate Military/Aerospace device (54LS169)is
available. Contacta National Semiconductor Sales
Office/Distributorfor specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6401–1
OrderNumber54LS169DMQB, 54LS169FMQB,54LS169LMQB,
DM54LS169AJ, DM54LS169AW,DM74LS169AMor DM74LS169AN
SeeNS Package Number E20A, J16A, M16A, N16Eor W16A
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
