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DM54LS164J-DM74LS164M-DM74LS164N
8-Bit Serial In/Parallel Out Shift Registers
TL/F/6398
54LS164/DM54LS164/DM74LS164
8-Bit
Serial
In/Parallel
Out
Shift
Registers
June 1989
54LS164/DM54LS164/DM74LS164
8-Bit Serial In/Parallel Out Shift Registers
General Description
These 8-bit shift registers feature gated serial inputsandan
asynchronous clear.Alow logic levelat either input inhibits
entryofthenew data,and resetsthefirst flip-floptothelow
levelatthe next clock pulse, thus providing complete con-
trol over incoming data.A high logic levelon either input
enablesthe other input, whichwill then determinethe statethefirst flip-flop.Dataat theserial inputs maybe changed
whilethe clockis highorlow,but only information meeting
the setupand holdtimerequirements willbe entered. Clock-
ing occursonthe low-to-high level transitionofthe clock
input.All inputsare diode-clampedto minimize transmis-
sion-line effects.
Features Gated (enable/disable) serial inputs Fully buffered clockand serial inputs Asynchronous clear Typical clock frequency36 MHz Typical power dissipation80 mW Alternate Military/Aerospace device (54LS164)is avail-
able. Contacta National Semiconductor Sales Office/
Distributorfor specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6398–1
Order Number 54LS164DMQB, 54LS164FMQB,
54LS164LMQB, DM54LS164J,DM54LS164W,
DM74LS164Mor DM74LS164N
SeeNS Package Number E20A,
J14A, M14A, N14Aor W14B
Function Table
Inputs Outputs
Clear Clock A B QA QB ... QH X X X L L ... L X X QA0 QB0 ... QH0 u H HHQAn ... QGn u LX L QAn ... QGn u XL L QAn ... QGneHigh Level (steadystate),LeLow Level (steady state)e Don’tCare(any input, includingtransitions)e Transitionfromlowtohighlevel
QA0,QB0,QH0eThe levelof QA,QB,orQH, respectively, beforethe
indicatedsteady-stateinput conditions wereestablished.
QAn,QGneThelevel ofQA orQG beforethemost recentu transitionof
the clock; indicatesa one-bitshift.
Logic Diagram
TL/F/6398–2
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
