DM74LS109AN ,Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary OutputsFeaturesnotdirectlyrelatedtothetransitiontimeoftherisingedgeofYAlternate Military/Aerospace device ..
DM74LS10M ,Triple 3-Input NAND GatesGeneral DescriptionThis device contains three independent gates each ofwhich performs the logic NAN ..
DM74LS10M ,Triple 3-Input NAND GatesFeaturesYAlternate Military/Aerospace device (54LS10) is avail-Thisdevicecontainsthreeindependentga ..
DM74LS10N ,Triple 3-Input NAND GateDM74LS10 Triple 3-Input NAND GateAugust 1986Revised March 2000DM74LS10Triple 3-Input NAND Gate
DM74LS112AM , Dual Negative-Edge-Triggered Master-Slave J-K Flip-FlopNational
Semiconductor
54LS112/DM54LS112A/DM74LS112A
Dual Negative-Edge-Triggered Master-Slave ..
DM74LS112AN ,7 V, dual negative-edge-triggered master-slave J-K flip-flop with preset, clear and complementary outputGeneral Description
This device contains two independent negative-edge-trig-
gered J-K flip-flo ..
DS21352 ,3.3V DS21352 and 5V DS21552 T1 Single Chip TransceiversFUNCTIONAL DESCRIPTION....83.2 DOCUMENT REVISION HISTORY...104.
DS21352DK ,T1 Single-Chip Transceiver Design Kit Daughter CardFEATURES The DS21352 design kit is an easy-to-use evaluation Demonstrates Key Functions of DS2135 ..
DS21352G ,3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers3.3V DS21352 and 5V DS21552T1 Single-Chip Transceivers
DS21352L ,3.3V DS21352 and 5V DS21552 T1 Single-Chip TransceiversFEATURES PIN ASSIGNMENT Complete DS1/ISDN–PRI/J1 transceiver functionality Long and Short haul L ..
DS21352L+ ,3.3V DS21352 and 5V DS21552 T1 Single Chip TransceiversFUNCTIONAL DESCRIPTION....83.2 DOCUMENT REVISION HISTORY...104.
DS21352LB+ ,3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers3.3V DS21352 and 5V DS21552T1 Single-Chip Transceivers
DM54LS109AJ-DM74LS109AN
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary Outputs
TL/F/6368
54LS109/DM54LS109A/DM74LS109A
Dual
Positive-Edge-Triggered
J-K
Flip-Flops
with
Preset,
Clear,
and
Complementary
Outputs
June 1989
54LS109/DM54LS109A/DM74LS109A
Dual Positive-Edge-Triggered J-K Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
geredJ-K flip-flops with complementary outputs. TheJand datais acceptedbythe flip-floponthe rising edgeofthe
clock pulse.The triggering occursata voltage levelandis
not directly relatedtothe transition timeofthe rising edgeof
the clock.The dataontheJandK inputs maybe changed
whilethe clockis highorlowas longas setup and hold
timesarenot violated.Alow logic levelonthe presetor
clear inputswillsetor resetthe outputs regardlessofthe
logic levelsofthe other inputs.
Features Alternate Military/Aerospace device (54LS109)is avail-
able. Contacta National Semiconductor Sales Office/
Distributorfor specifications
Connection Diagram
Dual-In-Line Package
TL/F/6368–1
Order Number 54LS109DMQB, 54LS109FMQB, DM54LS109AJ,
DM54LS109AW, DM74LS109AMorDM74LS109AN
SeeNS Package NumberJ16A, M16A, N16Eor W16A
Function Table
Inputs Outputs CLR CLK J K QQ X X X H L X X X L H X X X H* H* u LL L H u H L Toggle u LH Q0 Q0 u HH H L L X X Q0 Q0eHigh Logic LeveleLow Logic Levele EitherLoworHigh Logic Levele Rising Edgeof PulseeThis configurationis nonstable;thatis,itwillnot persist when preset
and/orclear inputs returntotheir inactive (high) state.e TheoutputlogiclevelofQ beforethe indicatedinput conditionswere
established.
ToggleeEach output changesto thecomplementofits previous levelon
each active transitionofthe clock pulse.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
