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DM54L93J
Decade/ Divide-by-12/ and Binary Counters
TL/F/6637
DM54L93
Decade,
Divide-by-12,
and
Binary
Counters
June 1989
DM54L93
Decade, Divide-by-12, and Binary Counters
General Description
Eachof these monolithic counters contains four master-
slave flip-flopsand additional gatingto providea divide-by-
two counteranda three-stage binary counterfor whichthe
count cycle lengthis divide-by-eight. use their maximum count length (decade, divide-by-
twelve,or four-bitbinary),theB inputis connected totheQA
output.The input count pulsesare appliedto inputA andthe
outputsareas describedinthe appropriate truth table.
Features Typical power dissipation16 mW Count frequency15 MHz
Connection Diagram
Dual-In-Line Package
TL/F/6637–1
Order Number DM54L93JorDM54L93W
SeeNS Package NumberJ14Aor W14B
Function Tables
COUNT SEQUENCE
(See NoteA)
Count Output QC QB QA L L L L L H L H L L H H H L L H L H H H L H H H L L L L L H H L H L H L H H H H L L H H L H H H H L H H H H
RESET/COUNT TRUTH TABLE (NoteB)
Reset Inputs Output
R0(1) R0(2) QD QC QB QA L L L L X COUNT L COUNT
NoteA: Output QAis connectedtoinputB
NoteB:HeHigh Level,LeLow Level,Xe Don’t Care.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
