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DM5473J-DM7473N
7 V, dual master-slave J-K flip-flop with clear and complementary output
National .
[ Semiconductor
5473/ DM5473/ DM7473
Dual Master-Slave J-K Flip-Flops with Clear
and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops after a complete clock
pulse. While the clock is low the slave is isolated from the
master. On the positive transition of the clock, the data from
the J and K inputs is transferred to the master. While the
clock is high the J and K inputs are disabled. On the nega-
tive transition of the clock. the data from the master is trans-
tened to the slave. The logic states of the J and K inputs
must not be allowed to change while the clock is high. Data
transfers to the outputs on the falling edge of the clock
pulse. A low logic level on the clear input will reset the out..
puts regardless of the logic states of the other inputs.
Features
I: Alternate Military/Aerospace device (5478) is available.
Contact a National Semiconductor Sales Office/Distrib-
utor for specifications.
Connection Diagram
DuaHn.Line Package
n ii, tit sub " 0: tit
" 13 12 In 10 a I
=l,.di' ---r.Lj'
t t la la 5 s I
cum cun kt Vcc CLttt CLRZ J2
TL/F/6525-1
Order Number 54730MQB, 5473FMOB, DM5473J, DM5473W or DM7473N
See NS Package Number J14A, N14A or W148
Function Table
Inputs Outputs
CLR CLK J K Q 6
L X X X L H
H .11 L L th ck
H J‘L H L H L
H IL L H L H
H J1. H H Toggle
H = High Logic Level
L = Low Logic Level
X ' Either Law or High Logic Level
J'L = Positive pulse data. the J and K inputs must be held constant while
the clock is high. Data is transferred to the outputs on the falling edge of the
dock pulse.
l = The output logic level before the Indicated input conditions were es-
tabllshed.
Toggle = Each output changes to the complement of its previous level on
each high level dock pulse.
Absolute Maximum Ratings (Note)
If MIIItary/Aorospace ttpotted devices are requlred,
please contact the National Setttlttortttutttttr Sales
OftlettfDhtrittutttra for avaliablmy and tspsttlfittatiorta.
Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range
DM54 and 54 --55''C to + 125''C
Storage Temperature Range
ty'C to + 70'C
-65''t? to +150’C
Recommended Operating Conditions
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarsn-
teed. The device should not be operated at these limits. The
parametric values defined in (he ''Etmrtriettl Characteristics"
table are not guaranteed at the absolute maximum ratings.
The ''Reeommtmdttd Operating Conditions" table will define
the conditions for actual device operation.
Symbol Parameter DM5473 DM7473 Units
Mln Nam Max Min Nam Max
Vcc Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
W. Low Level Input Voltage 0.8 0.8 V
10H High Level Output Current - 0.4 -0.4 mA
IOL Low Level Output Current 16 16 mA
fCLK Clock Frequency (Note 5) 0 15 0 15 MHz
tw Pulse Width Clock High 20 20
(Note 5) Clock Low 47 47 ns
Clear Low 25 25
tsu Input Setup Time (Note 1 & 5) 0 t 0 t ns
tH Input Hold Time (Note 1 & 5) 0 I O l ns
TA Free Air Operating Temperature - 55 125 0 70 (
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Condltlons Mln (N3: 2, Max Units
VI lnputClamp Voltage Vcc = Min, I. = -12 mA -t.5 V
VOH High Level Output Vcc = Min, 10H = Max 2.4 3.4 V
Voltage " = Max, VIH = Min
VOL Low Level Output Vcc = Min, lot. = Max 0.2 0.4 v
Voltage Ihre = Min, " = Max
k Input Current © Max Vcc = Max, V. = 5.5V 1 mA
Input Voltage
IIH High Level Input Vcc = Max J, K 40
Current V, = 2.4V Clock 80 “A
Clear 80
In. Low Level Input VCC = Max J, K -1.6
Current V) = 0.4V Clock -3.2 mA
Clear - 3.2
los Short Circuit VCC = Max DM54 - 20 - 55 m A
Output Current (Note 3) DM74 _ 18 - 55
loc Supply Current Vcc = Max, (Note 4) 18 34 mA
Note 1: The symbol it, l) indicates the edge or the clock pulse is used far reference: it) for rising edge, (l) fortalling edge‘
Note 2: All typical: are at Vcc = SV, TA am 25°C.
Not. 3: Not more than one output should be shorted at a time.
Note 4: With all outputs open, '00 is measuted with me a and ta outputs high in turn. At the time of measurement the clock input grounded.
Note s.. TA = 25’C and Vcc " 5V.
Switching Characteristics at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
From (Input) RL = 400n
Symbol Parameter To (Output) th. = " pF Unlls
Min Max
fMAx Maximum Clock 1 5 MHz
Frequency
tPHL Propagation Delay Time Clear 40 ns
High to Low Level Output to Q
tpLH Propagation Delay Time Clear 25 ns
Low to High Level Output to G
tPHL Propagation Delay Time Clock to 40 ns
High to Low Level Output 0 or 6
tle Propagation Delay Time Clock to 25 ns
Low to High Level Output 0 or G
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
5473DMQB - product/5473qub?HQS=TI-nulI-null-dscatalog-df-pf-nuII-wwe
5473FMQB - product/5473fmqb?HQS=T|—null-null-dscataIog-df-pf-null-wwe
DM5473J - productldm5473j?HQS=T|-nulI—nu|I—dscatalog-df-pf-nulI-wwe
DM5473W - product/dm5473w?HQS=T|-nu|I-nuII-dscatalog-df-pf-nuII-wwe
DM7473N - product/dm7473n?HQS=T|-nu|I-nulI-dscatalog-df-pf—nuII-wwe
