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DM54161J-DM74161N
Synchronous 4-Bit Counters
TL/F/6551
DM54161/DM74161/DM74163
Synchronous
4-Bit
Counters
October 1992
DM54161/DM74161/DM74163
Synchronous 4-Bit Counters
General Description
These synchronous, presettable counters featurean inter-
nal carry look-aheadfor applicationin high-speed counting
designs. The 161 and 163are 4-bit binary counters. The
carry outputis decodedby meansofa NOR gate, thuspre-
venting spikes duringthe normal counting modeof opera-
tion. Synchronous operationis providedby havingallflip-
flops clocked simultaneouslysothatthe outputs changeco-
incident with each other whenso instructedbythe count-
enable inputsand internal gating. This modeof operation
eliminatesthe output counting spikes whichare normally
associated with asynchronous (ripple clock) counters.A
buffered clock input triggersthe four flip-flopsonthe rising
(positive-going) edgeofthe clock input waveform.
These countersare fully programmable;thatis,the outputs
maybe presetto either level.As presettingis synchronous,
settingupalow levelatthe load input disablesthe counter
and causesthe outputsto agree withthe setup data after
the next clock pulse, regardlessofthe levelsofthe enable
input.The clear functionforthe161is asynchronous;anda
low levelatthe clear input setsallfourofthe flip-flopout-
puts low, regardlessofthe levelsof clock, load,or enable
inputs.The clear functionforthe163is synchronous;anda
low levelatthe clear input setsallfourofthe flip-flopout-
putslow afterthe next clock pulse, regardlessofthe levelsthe enable inputs. This synchronous clear allowsthe
count lengthtobe modified easily,as decodingthe maxi-
mum count desired canbe accomplished with one
external NAND gate. The gate outputis connectedtothe
clear inputto synchronously clearthe countertoalllowout-
puts. Low-to-high transitionsatthe clear inputofthe163are
also permissible, regardlessofthe logic levelsonthe clock,
enable,or load inputs.
The carry look-ahead circuitry providesfor cascading coun-
tersfor n-bit synchronous applications without additional
gating. Instrumentalin accomplishingthis functionaretwo
count-enable inputs anda ripple carry output. Both count-
enable inputs(PandT) must behighto count,and inputTis
fed forwardto enablethe ripple carry output.The ripplecar- outputthus enabledwill producea high-level output pulse
witha duration approximately equaltothe high-level portiontheQA output. This high-level overflow ripple carry pulse
canbe usedto enable successive cascaded stages. High-
to-low-level transitions atthe enablePorT inputsofthe161
through163 may occur, regardlessofthe logic levelonthe
clock.
Features Synchronously programmable Internal look-aheadforfast counting Carry outputfor n-bit cascading Synchronous counting Load controlline Diode-clamped inputs
Connection Diagram
Dual-In-Line Package
TL/F/6551–1
Order Number DM54161J,DM54161W,
DM74161Nor DM74163N
SeeNS PackageNumberJ16A, N16Eor W16A
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
