DM3730CUS100 ,Digital Media Processor 423-FCBGA 0 to 90Bus• Glueless Interface to Common VideoDecoders– Up to 8 Chip Select Pins With128M-Byte Address Spa ..
DM413 , 3-CHANNEL CONSTANT CURRENT LED DRIVERS WITH PROGRAMMABLE PWM OUTPUTS
DM48S3.3-4000 , Single and Dual Output 15 Watt DC/DC Converter 2:1 Wide Input Voltage Range
DM5400J ,Quad 2-Input NAND Gates5400/DM5400/DM7400Quad2-InputNANDGatesJune19895400/DM5400/DM7400Quad2-InputNANDGatesGeneralDescript ..
DM5402J ,Quad 2-Input NOR Gates5402/DM5402/DM7402Quad2-InputNORGatesJune19895402/DM5402/DM7402Quad2-InputNORGatesGeneralDescriptio ..
DM5403J ,Quad 2-Input NAND Gates with Open-Collector OutputsDM5403/DM7403Quad2-InputNANDGateswithOpen-CollectorOutputsJune1989DM5403/DM7403Quad2-InputNANDGates ..
DS1556P-70 ,1M, Nonvolatile, Y2K-Compliant Timekeeping RAMPIN DESCRIPTION A0–A16 - Address Input DQ0–DQ7 - Data Input/Outputs IRQ/FT - Interrupt, Freque ..
DS1556P-70 ,1M, Nonvolatile, Y2K-Compliant Timekeeping RAMFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Cont ..
DS1556P-70 ,1M, Nonvolatile, Y2K-Compliant Timekeeping RAM DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
DS1556W-120 ,1M, Nonvolatile, Y2K-Compliant Timekeeping RAMFEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Cont ..
DS1556WP+120 ,1M, Nonvolatile, Y2K-Compliant Timekeeping RAMPIN DESCRIPTION A0–A16 - Address Input DQ0–DQ7 - Data Input/Outputs IRQ/FT - Interrupt, Freque ..
DS1556WP-120 ,1M, Nonvolatile, Y2K-Compliant Timekeeping RAMPIN DESCRIPTION A0–A16 - Address Input DQ0–DQ7 - Data Input/Outputs IRQ/FT - Interrupt, Freque ..
DM3730CUS100
Digital Media Processor
DM3730, DM3725
www.ti.com SPRS685D–AUGUST 2010–REVISED JULY 2011
DM3730, DM3725
Digital Media Processors
Checkfor Samples: DM3730, DM3725 DM3730, DM3725 Digital Media Processors
1.1 Features
123456 Load-Store Architecture With•
DM3730/25 Digital Media Processors: Non-Aligned Support–
Compatible with OMAP™3 Architecture •
64 32-Bit General-Purpose Registers–
ARM®
Microprocessor (MPU) Subsystem •
Instruction Packing Reduces Code Size•
Upto 1-GHz ARM®
Cortex™-A8 Core All Instructions ConditionalAlso supports 300, 600, and 800-MHz
operation •
Additional C64x+TM Enhancements NEON™ SIMD Coprocessor –
Protected Mode Operation High Performance Image, Video, Audio –
Expectations Support for Error
(IVA2.2TM) Accelerator Subsystem Detection and Program Redirection Upto 800-MHz TMS320C64x+TM DSP Core –
Hardware Support for Modulo Loop
Also supports 260, 520, and 660-MHz Operation
operation –
C64x+TM L1/L2 Memory Architecture Enhanced Direct Memory Access (EDMA) •
32K-Byte L1P Program RAM/Cache
Controller (128 Independent Channels) (Direct Mapped) Video Hardware Accelerators •
80K-Byte L1D Data RAM/Cache (2-Way POWERVR SGX™ Graphics Accelerator Set- Associative)
(DM3730 only) •
64K-Byte L2 Unified Mapped RAM/Cache Tile Based Architecture Delivering upto (4- Way Set-Associative) MPoly/sec •
32K-Byte L2 Shared SRAM and 16K-Byte Universal Scalable Shader Engine: L2 ROM
Multi-threaded Engine Incorporating Pixel –
C64x+TM Instruction Set Featuresand Vertex Shader Functionality •
Byte-Addressable (8-/16-/32-/64-Bit Data) Industry Standard API Support: •
8-Bit Overflow ProtectionOpenGLES 1.1 and 2.0, OpenVG1.0 •
Bit-Field Extract, Set, Clear•
Fine Grained Task Switching, Load •
Normalization, Saturation, Bit-CountingBalancing, and Power Management •
Compact 16-Bit Instructions High Quality Image •
Additional Instructionsto Support Complex Multiplies –
External Memory Interfaces:TM DSP Core (SDRC) Memory Controller With 1G-Byte Space Supports –
Interfaces Quad 8-bit, SDRAM MemoryArithmetic
Rotation Engine16x 16-Bit General Purpose Memory per Clock
(GPMC) (16-Bit –
16-bit Address/Data notice concerning availability, standard and usein critical applicationsof Texas and disclaimers thereto appearsatthe endof this data sheet.
