DG401DY ,Monolithic CMOS Analog SwitchesDG401, DG403, DG405Data Sheet June 1999 File Number 3284.6Monolithic CMOS Analog Switches
DG401DY ,Monolithic CMOS Analog SwitchesELECTRICAL CHARACTERISTICS(V+ = 15V, V- = -15V, V = +5V, GND = 0V, V = +2.4V, V = +0.8V, T = T to T ..
DG401DY ,Monolithic CMOS Analog SwitchesFeaturesThe DG401, DG403 and DG405 monolithic CMOS analog• ON Resistance (Max) . . . . . . . . . . ..
DG401DY+ ,Improved, Dual, High-Speed Analog SwitchesELECTRICAL CHARACTERISTICS(V+ = 15V, V- = -15V, V = +5V, GND = 0V, V = +2.4V, V = +0.8V, T = T to T ..
DG403AK ,Improved / Dual / High-Speed Analog SwitchesDG401/DG403/DG40519-4727; Rev 2; 6/99Improved, Dual, High-Speed Analog Switches_______________
DG403AK/883 , Low-Power, High-Speed CMOS Analog Switches
DRA125-330-R , High Power Density, High Efficiency, Shielded Inductors
DRA127-151-R , High Power Density, High Efficiency, Shielded Inductors
DRA2143E0L , DRA2143E Silicon PNP epitaxial planar type
DRA5114E0L , DRA5114E Silicon PNP epitaxial planar type
DRA74-4R7-R , High Power Density, High Efficiency, Shielded Inductors
DRDNB16W-7 , COMPLEX ARRAY FOR RELAY DRIVERS
DG401CJ-DG401DJ-DG401DY-DG403AK-DG403CJ-DG403CY-DG403DJ-DG403DY-DG403DY.-DG405CY-DG405DJ-DG405DY
Improved / Dual / High-Speed Analog Switches
_______________General DescriptionMaxim's redesigned DG401/DG403/DG405 analog
switches now feature guaranteed low on-resistance
matching between switches (2Ωmax) and guaranteed
on-resistance flatness over the signal range (3Ωmax).
These low on-resistance switches (20Ωtyp) conduct
equally well in either direction and are guaranteed to
have low charge injection (15pC max). The new design
offers lower off leakage current over temperature (less
than 5nA at +85°C).
The DG401/DG403/DG405 are dual, high-speed
switches. The single-pole/single-throw DG401 and
double-pole/single-throw DG405 are normally open
dual switches. The dual, single-pole/double-throw
DG403 has two normally open and two normally closed
switches. Switching times are 150ns max for tONand
100ns max for tOFF, with a maximum power consump-
tion of 35µW. These devices operate from a single
+10V to +30V supply, or bipolar supplies of ±4.5V to
±20V. Maxim's improved DG401/DG403/DG405 are
fabricated with a 44V silicon-gate process.
________________________ApplicationsSample-and-Hold CircuitsTest Equipment
Guidance and Control SystemsHeads-Up Displays
Communications SystemsPBX, PABX
Battery-Operated SystemsAudio Signal Routing
Military Radios
______________________New FeaturesPlug-In Upgrade for Industry-Standard
DG401/DG403/DG405Improved rDS(ON)Match Between Channels (2Ωmax)Guaranteed rFLAT(ON)Over Signal Range (3Ωmax)Improved Charge Injection (15pC max)Improved Off Leakage Current Over Temperature
(<5nA at +85°C)
__________________Existing FeaturesLow rDS(ON)(30Ωmax)Single-Supply Operation +10V to +30V
Bipolar-Supply Operation ±4.5V to ±20VLow Power Consumption (35µW max)Rail-to-Rail Signal Handling CapabilityTTL/CMOS-Logic Compatible
______________Ordering Information
Ordering Information continued on last page.*Contact factory for dice specifications.
DG401/DG403/DG405
Improved, Dual, High-Speed Analog Switches
_____________________Pin Configurations/Functional Diagrams/Truth Tables19-4727; Rev 2; 6/99
Improved, Dual, High-Speed Analog Switches
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(V+ = 15V, V- = -15V, VL= +5V, GND = 0V, VINH= +2.4V, VINL= +0.8V, TA= TMIN to TMAX, unless otherwise noted.)
DG401/DG403/DG405
Note 1:Signals on S, D or IN exceeding V+ or V- are clamped by internal diodes. Limit forward current to maximum
current rating.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Referenced to V-
V+.......................................................................................44V
GND...................................................................................25V.................................................(GND - 0.3V) to (V+ + 0.3V)
Digital Inputs, VS, VD(Note 1).......(V- - 2V) to (V+ + 2V) or 20mA
(whichever occurs first)
Continuous Current (any terminal)......................................30mA
Continuous Current, S or D.................................................20mA
Peak Current, S or D
(pulsed at 1ms, 10% duty cycle max)..........................100mA
Continuous Power Dissipation (TA= +70°C)
16-Pin Plastic DIP(derate 10.53mW/°C above +70°C)...842mW
16-Pin Narrow SO (derate 8.70mW/°C above +70°C)...696mW
16-Pin CERDIP (derate 10.00mW/°C above 70°C).......800mW
20-Pin LCC (derate 9.09mW/°C above +70°C)............727mW
Operating Temperature Ranges
DG40_C_.............................................................0°C to +70°C
DG40_D_..........................................................-40°C to +85°C
DG40_A_........................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
DG401/DG403/DG405
Improved, Dual, High-Speed Analog Switches
ELECTRICAL CHARACTERISTICS (continued)(V+ = 15V, V- = -15V, VL= +5V, GND = 0V, VINH= +2.4V, VINL= +0.8V, TA= TMIN to TMAX, unless otherwise noted.)
Note 2:This data sheet uses the algebraic convention, where the most negative value is a minimum and the most positive value is a
maximum.
Note 3:Guaranteed by design.
Note 4:ΔrON= ΔrON(max) - ΔrON(min). On-resistance match between channels and flatness are guaranteed only with specified
voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured at the
extremes of the specified analog signal range.
Note 5:Off isolation = 20log (VS/VD), VD= output, VS= input to off switch.
Note 6:Between any two switches.
Note 7:Leakage parameters IS(OFF), ID(OFF), and ID(ON)are 100% tested at the maximum rated hot temperature and guaranteed by
correlation at +25°C.
DG401/DG403/DG405
Improved, Dual, High-Speed Analog Switches
__________________________________________Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
DG401/DG403/DG405
Improved, Dual, High-Speed Analog Switches
__________Applications Information_____________________Pin DescriptionFigure 1. Overvoltage Protection Using External Blocking Diodes
Operation with Supply Voltages
Other than ±15VThe DG401/DG403/DG405 switches operate with
±4.5V to ±20V bipolar supplies or with a +10V to +30V
single supply. In either case, analog signals ranging
from V+ to V- can be switched. The Typical Operating
Characteristicsgraphs illustrate typical analog-signal
and supply-voltage on-resistance variations. The usual
on-resistance temperature coefficient is 0.5%/°C (typ).
Logic InputsThese devices operate with a single positive supply or
with bipolar supplies. They maintain TTL compatibility
with supplies anywhere in the ±4.5V to ±20V range as
long as VL= +5V. If VLis connected to V+ or another
supply at voltages other than +5V, the devices will
operate at CMOS-logic-level inputs.
Overvoltage ProtectionProper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute
maximum ratings because stresses beyond the listed
ratings may cause permanent damage to the devices.
Always sequence V+ on first, followed by VL, V-, and
logic inputs. If power-supply sequencing is not
possible, add two small, external signal diodes in
series with supply pins for overvoltage protection
(Figure 1). Adding diodes reduces the analog-signal
range to 1V below V+ and 1V below V-, without affect-
ing low switch resistance and low leakage
characteristics. Device operation is unchanged, and
the difference between V+ and V- should not exceed
+44V.
DG401/DG403/DG405
Improved, Dual, High-Speed Analog Switches
______________________________________________Timing Diagrams/Test CircuitsFigure 2. Switching Time
Figure 4. Charge Injection
Figure 3. Break-Before-Make Interval
