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DALC208SC6
LOW CAPACITANCE DIODE ARRAY
DALC208SC6February 2002 - Ed: 5C
IEC61000-4-2 level4
MIL STD 883C- Method 3015-6
(human body test) class3
COMPLIES WITHTHEFOLLOWING STANDARDS: PROTECTION OF4 LINES PEAK REVERSE VOLTAGE:
VRRM=9V per diode VERY LOW CAPACITANCE PER DIODE: 5pF VERY LOW LEAKAGE CURRENT:IR <1μA
FEATURES
FUNCTIONAL DIAGRAMLOW CAPACITANCE
DIODE ARRAY
Application Specific Discretes
A.S.D.TM
Where ESD and/or over and undershoot
protectionfor datalinesis required: Sensitive logic input protection Microprocessor based equipment Audio/ Video inputs Portable electronics Networks ISDN equipment USB interface
MAIN APPLICATIONSThe DALC208SC6 diode arrayis designedto
protect components which are connectedto data
and transmission lines from overvoltages caused electrostatic discharge (ESD) or other
transients.Itisa rail-to-rail protection device also
suited for overshoot and undershoot suppression sensitive logic inputs.
The low capacitance of the DALC208SC6
prevents from significant signal distortion.
DESCRIPTION Cost-effectiveness comparedto discrete solution High efficiencyin ESD suppression No significant signal distortion thanksto very low
capacitance High reliability offeredby monolithic integration Lower PCB area consumption versus discrete
solution
BENEFITS
DALC208SC6
ABSOLUTE MAXIMUM RATINGS (Tamb= 25°C).
Note2: The dynamical behavioris describedinthe Technical Information section,on page4.
ELECTRICAL CHARACTERISTICS (Tamb= 25°C).
Note3: Input capacitance measurement
Note1: device mountedon FR4 PCB with recommended footprint dimensions.
THERMAL RESISTANCE
DALC208SC60.001 0.01 0.1 1 10 100 10000
tp(ms)
IFSM(A)
Fig.1: Maximum non-repetitive peak forward current
versus rectangular pulse duration(Tj initial= 25°C). 10152025300.1
Vcl(V)
Ipp(A)
Fig. 2: Reverse clamping voltage versus peak
pulse current(Tj initial= 25°C), typical values.
Rectangular waveformtp= 2.5 μs. 50 75 100 125 1500.01
Tj(°C)
IR(μA)
Fig.3: Variationof leakage current versus junction
temperature (typical values).
012 34 55.0
VR(V)
C(pF)
Fig.4: Input capacitance versus reverse applied
voltage (typical values). 2 4 6 8 10 12 14 16 18 200.1
VFM(V)
IFM(A)
Fig.5: Peak forward voltage drop versus peak for-
ward current (typical values).
Rectangular waveformtp= 2.5 μs.
DALC208SC6The DALC208SC6is particularly optimized to
perform surge protection based on the railto rail
topology.
The clamping voltage VCL can be calculated as
follow:
VCL+=VREF2 +VF for positive surges
VCL-= VREF1- VF for negative surges
with: VF =Vt+ rd.Ip
(VF forward drop voltage)/ (Vt forward drop
threshold voltage)
According to the curve Fig.5 on page 3, we
assume that the valueof the dynamic resistanceof
the clamping diodeis typicallyrd= 0.7Ω andVt=
1.2V.
For an IEC61000-4-2 surge Level4 (Contact
Discharge: Vg=8kV, Rg=330Ω), VREF2= +5V,
VREF1= 0V, andifin first approximation, we
assume that: Ip=Vg/Rg′ 24A.
So, we find:
VCL+′ +23V
VCL-′ -18V
Note: the calculations do not take into account
phenomena dueto parasitic inductances
APPLICATION EXAMPLE we consider that the connections from the pin
REF2to VCC and from REF1to GND are doneby
two tracksof 10mm long and 0.5mm large; we
assume that the parasitic inductancesof these
tracks are about 6nH. when an IEC61000-4-2 surge occurs, dueto
the rise timeof this spike (tr=1ns), the voltage VCL
hasan extra value equalto Lw.dI/dt.
The dI/dtis calculated as: di/dt= Ip/tr′24 A/ns
is: Lw.di/dt=6x24′ 144V taking into account the effectof these parasitic
inductances dueto unsuitable layout, the clamping
voltage willbe:
VCL+= +23+ 144′ 167V
VCL-= -18- 144′ -162V can reduce as much as possible these
phenomena with simple layout optimization.
It’s the reason why some recommendations have be followed (see paragraph “Howto ensurea
good ESD protection”).
TECHNICAL INFORMATION
SURGE PROTECTION
Fig. A1: ESD behavior; parasitic phenomena dueto unsuitable layout.
DALC208SC6
HOW TO ENSUREA GOOD ESD PROTECTIONWhile the DALC208SC6 providesa high immunity ESD surge, an efficient protection dependson
the layoutof the board.In the same way, with the
railto rail topology, the track from the VREF2 pinto
the power supply +VCC and from the VREF1 pinto
GND must be as short as possible to avoid
overvoltages dueto parasitic phenomena (see Fig.
A1).
It’s often harderto connect the power supply near the DALC208SC6 unlike the ground thanksto
the ground plane that allowsa short connection. ensure the same efficiencyfor positive surges
when the connections can’t be short enough, we
recommendto put closeto the DALC208SC6,
between VREF2 and ground,a capacitanceof
100nFto prevent from these kindsof overvoltage
disturbances (see Fig. A2).
The addof this capacitance will allowa better
protection by providing during surgea constant
voltage.
Fig. A3, A4a and A4b show the improvementof the
ESD protection accordingto the recommendations
described above.
Fig. A2: ESD behavior: optimized layout and adda capacitanceof 100nF. main precautionto takeisto put the protection
device closerto the disturbance source (generally
the connector).
Fig. A3: ESD behavior: measurements conditions
(with coupling capacitance).
Fig. A4a: Remaining voltage after the
DALC208SC6 during positive ESD surge.
Fig. A4b: Remaining voltage after the
DALC208SC6 during negative ESD surge.
Note: The measurements have been done withthe DALC208SC6
inopen circuit.
DALC208SC6
CROSSTALK BEHAVIOR Crosstalk phenomenaThe crosstalk phenomena are dueto the coupling
between2 lines. The coupling factor (β12or β21)
increases when the gap across lines decreases,
particularlyin silicon dice.In the example above
the expected signalon load RL2is α2VG2,in fact
the real voltageat this point has gotan extra value
β21VG1. This partof the VG1 signal represents the
effectof the crosstalk phenomenonof the line1on
the line2. This phenomenon hasto be taken into
account when the drivers impose fast digital data high frequency analog signalsin the disturbing
line. The perturbed line will be more affectedifit
works with low voltage signal or high load
impedance (few kΩ). The following chapters give
the valueof both digital and analog crosstalk.
Digital CrosstalkFigure A5 shows the measurement circuit usedto
quantify the crosstalk effectina classical digital
application.
Figure A6 shows thatin sucha condition: signal
from0Vto5V anda rise timeof5 ns, the impacton
the disturbed lineis less than 100mV peakto peak. data disturbance was notedon the concerned
line. The same results were obtained with falling
edges.
Note: Themeasurements have beendoneinthe worst casei.e.on
two adjacentcells (I/O1& I/O4).
Fig. A4: Crosstalk phenomena.
Fig. A5: Digital crosstalk measurements.
Fig. A6: Digital crosstalk results.
