DAC8841-GBC ,0.3-7.0V; octal 8-bit, 2-quadrant multiplying, CMOS trimDAC. For dynamic level adjustment, trimmer replacementSPECIFICATIONS
Input Clock Pulse Width tera, ter, 80 ns
Data Setup Time tos 40 ns
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DAC8841FS-DAC8841-GBC
0.3-7.0V; octal 8-bit, 2-quadrant multiplying, CMOS trimDAC. For dynamic level adjustment, trimmer replacement
ANALOG
DEVICES
8-Bit Octal, 2-iluadrtmt
Multiplying, CMOS Trimlylt
DAO-8841
FEATURES
Replaces 8 Potentiometers
Operates From Single +5 V Supply
1 MHz 2-0uadrant Multiplying Bandwidth
No Signal Inversion
Eight Individual Channels
3-Wire Serial Input
soo kHz Update Data Loading Rate
+3 Volt Output Swing
Midsealo Preset
Low 95 mW Power Dissipation
APPLICATIONS
Trimmer Replacement
Dynamic Level Adjustment
Special Waveform Generation and Modulation
Programmable Gain Amplifiers
GENERAL DESCRIPTION
The DAC-884l provides eight general purpose digitally controlled
voltage adjustment devices. The TrimDAC" capability replaces
the mechanical trimmer function in new designs. It is ideal for
ac or dc gain control of up to 1 MHz bandwidth signals.
Internally the DAC-8841 contains eight voltage output CMOS
digital-to-analog conveners, each with separate reference inputs.
Each DAC has its own DAC register which holds its output
state. These DAC registers are updated from an internal serial-
to-parallel shift register which is loaded from a standard 3-wire
serial input digital interface. Twelve data bits make up the data
word clocked into the serial input register. This data word is
decoded where the first 4 bits determine the address of the DAC
register to be loaded with the last 8 bits of data. A serial data
output pin at the opposite end of the serial register allows sim-
ple daisy-chaining in multiple DAC applications without addi-
tional external decoding logic.
TrimDAC is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DECODED
v ADDRESS
LOAD LOGIC
DATA DAC
4/ 8F. REGISTER
SERIAL ,
sm o- REGISTER 1 DACH / V001”
CLK ed, . DAC'8841
GND soo PRESET VREFL
The DAC-884l consumes only 95 mW from a +5 V power sup-
ply. For dual polarity applications see the DAC-8840 which pro-
vides full 4-quadrant-multiplying :3 V signal capability while
operating from t5 V power supplies.
The DAC-884l is available in 24-pin plastic DIP, cerdip, and
SOIC-24 packages. For MIL-STD/883 applications, contact
ADI sales for the DAC-884IBW/883 data sheet which specifies
operation over -55''C to + 125°C.
One Technology Way, P.O. Box 9106, Norwood, MA 0206b9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 wa: 710/394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
DAC-8841 -SPE0lFliym0lG
Von = +5 ll, itll me = +1.5 ll, VREF" = W, T“ = -4ir'll to +85''0 apply for MO-
ELECTRICAL CHARACTERISTICS 8841F, unless otherwise noted.
Parameter Symbol Conditions Min Typ Max Units
STATIC ACCURACY All Specifications Apply for DACs A, B, C,
D, E, F, G, H
Resolution N 8 Bits
Integral Nonlinearity INL Note 1 t 1/2 t 1.5 LSB
Differential Nonlinearity DNL All Devices Monotonic, Note 1 tl LSB
Half-Scale Output Voltage VHS P-R = 0 V, Sets D = 80H 1.475 1.500 1.525 V
Zero-Scale Output Voltage st Digital Code = 00H 20 100 mV
Output Voltage Drift TCVHS tm = 0 V, Sets D = 8h, 10 pV/°C
SIGNAL INPUTS Applies to All Inputs VINX or VREFL
Input Voltage Range IVR 0 1.5 V
Input Resistance Rm D = 55rs; Code Dependent 4 10 kit
Input Capacitance Cm Code Dependent 19 30 pF
REF Low Resistance RREFL D = Aiha; Code Dependent 0.3 0.75 k0.
REF Low Capacitance CREFL Code Dependent 190 250 pF
DAC OUTPUTS Applies to All Outputs Vou-rX
Voltage Range OVR RL = 10 kn 0 3 V
Output Current IOUT AVOUT < 25 mV, vmx = 1.375v, P-R = o v t5 7 mA
Capacitive Load G. No Oscillation 200 pF
DYNAMIC PERFORMANCE Applies to All DACs
Multiplying Gain Bandwidth GBW VINX = 100 mV p-p + 1.0 V dc 1 2.5 MHz
Slew Rate Measured 10% to 90%
+SR AVOUTX = +3 V 1.3 4.0 V/ps
-SR AVOUTX = -3 V 1.3 2.5 V/ps
Total Harmonic Distortion THD VmX = 1 V p-p + 1.0 V dc, D = FFH, f = 1 kHz, 0.01 %
ha, = 80 kHz
Spot Noise Voltage er: f = 1 kHz 0.17 uwvm
Output Settling Time ts tl LSB Error Band, 810 to 25510 3.5 6 pus
Channel to Channel Crosstalk Cr Measured Between Adjacent Channels, f = 100 kHz 60 70 dB
Digital Feedthrough Q VREFL = +1.5 v, D = 0 to FF,, 6 INS
POWER SUPPLIES
Positive Supply Current IDD P-R = 0 V 19 26 mA
Power Dissipation Pmss 95 130 mW
DC Power Supply Rejection Ratio PSRR P-R = 0 V 0.01 %/%
Power Supply Range PSR iron 4.75 5.00 5.25 V
DIGITAL INPUTS
Logic High Vrre 2.4 V
Logic Low Va. 0.8 V
Input Current IL t10 wh
Input Capacitance Cm 8 pF
Input Coding Binary
DIGITAL OUTPUT
Logic High Vor, Ion = -0.4 mA 3.5 V
Logic Low Voc loc = 1.6 mA 0.4 V
TWIN G SPECIFICATIONS
Input Clock Pulse Width ten, ch. . 80 ns
Data Setup Time tos 40 ns
Data Hold Time tore 20 ns
CLK to SDO Propagation Delay teo 120 ns
DAC Register Load Pulse Width tco _ 70 ns
Preset Pulse Width tpR 50 ns
Clock Edge to Load Time tdrum 30 ns
Load Edge to Next Clock Edge tcocr 60 ns
1INL and DNL tests do not include operation at codes 0 thru 7 due to zero-scale output voltage. For bias voltages above 100 mV on VREFL, INL and DNL are
maintained over all codes.
Specifications subject to change without notice.
-2- REV. A
DAC-8841
WAFER TEST LIMITS: h, = +5 ll, All 1Glt = +1.5 Y, me = il v.1A = 25T, unless otherwise noted.
DAC-8841GBC
Parameter Symbol Conditions Limits Units
Integral Nonlinearity INL Note 1 -t 1.5 LSB max
Differential Nona'earity DNL All Devices Monotonic, Note 1 tl LSB max I
Half-Scale Output Voltage VHS W = O V, Sets D = 80H 1.475/1.525 V min/max
Input Resistance (VINX) RIN D = 55H; Code Dependent 4 k0 min
REF Low Resistance RREFL D = ABu; Code Dependent 0.3 kn min
DAC Output Voltage Range OVR RL = 10 kn 3 V min
DAC Output Current IOUT AVOUT < 25 mV t-5 mA min
Slew Rate Measured 10% to 90%
Positive SR+ AVOUTX = +3 V 1.3 V/ws min
Negative SR- AVOUTX = -3 V 1.3 V/ws min
Positive Supply Current IDD FK" = 0 V 26 mA max
DC Power Supply Rejection Ratio PSRR FIR = 0 V, AVDD = t5% 0.01 %l% max
Logic Input High Vo, 2.4 V min
Logic Input Low V11. 0.8 V max
Logic Input Current IL t 10 " max
Logic Output High Vor, lor, = -0.4 mA 3.5 V min
Logic Output Low Vor, loc - 1.6 mA 0.4 V max
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
sm t'cyA3xaax-AtxAoy:iarxmsxms-yDayCDvy:txt)Ctutsso x
1 DAC REGISTER LOAD _
Lo o 'y')
25.__\_
[£111 SERIAL DATA INPUT TNING
(PR = "I," v.N * 1.5V, VREF L = mo
(DATA IN) o
(DATA out) a
ts----
VOUT (FFN)
' Mn) _-------------------------------
PRESET TIMING
REV. A
I L" LSB ERROR BAND
Figure 1. Timing Diagram
l t " LSB ERROR BAND
DAC-8841
ABSOLUTE MAXIMUM RATINGS
cr, = '25'C, unless otherwise noted)
Vos, to GND ...................... -0.3 V, +7 V
VINX to GND ............................ Vor,
VREFL to GND ........................... FL,
VOUTX to GND ........................... Vor,
Short Circuit Iom-X to GND .............. Continuous
Digital Input & Output Voltage to GND ........... VDD
Operating Temperature Range
Extended Industrial: DAC-8841F ....... -40''C to +85°C
Maximum Junction Temperature (T, max) ........ +150°C
Storage Temperature ............... -65"C to + 150°C
Lead Temperature (Soldering, 10 sec) ........... +300°C
Package Power Dissipation .......... (T, Max - TAM)“
Thermal Resistance 61A
Cerdip .............................. 64°C/W
P-DIP .............................. 57°C/W
SOIC-24 ............................. 70°C/W
DAC-8841 PIN DESCRIPTION
PIN CONFIGURATIONS
"ourc E . V Ei VOUTD
Vour B E Ei Mm c
VourA E
VINE E
VREFL E
VIN E E
VIN F E
VourE E
VOUTF E
VOUTG E
DAC-8841
TOP VIEW
(Not to Scale)
ii] vIN D
Ei Von
Ei GND
E] soo
El CLK
El vm H
E] vIN G
E] VOUT“
DICE CHARACTERISTICS
Pln Mnemonic Descrlptlon DIE SIZE 0.117 X 0.185 inch, 21,645 sq. mils
1 VoorC WWW $7.1: L4t,tl,',estel,'i11ysqi,C,t,,, toV
2 VomB DAC B Output DD‘
3 VowA DAC A Output , , 8 , 7 f
4 vma DAC B Reference Input l 1 I l cal 1
s va me A Reference Input
6 ' DAC Input Reference Low a 1: tlt 1: lit
7 F-tt Preset Input, Active Low, All DAC Registers :5 g g h
= 80" ll- a g g a 2
e va me E Raferonco Input " , g g a
9 vms DAC F Reference Input " " a l
" vow: me E Output 'i g g i,
" VomF DAC F Output il tl g ll
" vows DAC G Output 13- g , _ g P 24
" va DAC H Output 14-- - ta , ' , ' 33 9 ~23
" bravd7 DAC G Reference Input Gil a o ging' i 's' . _ 22
" 1fmH DAC H Rofaranco Input . 1 I 1
" LD Load DAC Register Strobe, Active High Input tls ,l, 1', d ,L i, l
that Transfer: the Data Bits from the Serial
Input Register into the Decoded DAC
Registar.Stre Tablel 1. Vourc 13. VOUTH
" CLK Serial Clock Input, Poshlve Edge Triggered 2. VOUTB 14. VING
18 SDO Serial Data Output. Active Totem Polo Output 3. VourA 15. VINH
" GND Ground 4. VINB 16. LD
20 SDI Serial Data Input 5. VINA 17. CLK
21 1fuo Positive 5 V Power Supply 6. MEFL 18. SDO
22 vmo DAC D Reference Input 7. PR 19. GND
23 VmC DAC C Reference Input 8. VmE 20. SDI
" vomn me D Output S. VmF 21. Vor,
1o. vows 22. vmo
11. lfou,F 23. vmc
12. vows 24. VOUTD
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.
G!TimilIIllml
REV. A
DAC-8841
ORDERING GUIDE
Model Temperature Range Package Option
DAC8841FP -40oc to +85°C Plastic DIP
DAC8841FW -40''C to +85°C Ctrdip
DAC884IFS -400C to +85°C SOIC
DAC884IGBC -25''C Dice
For devices processed in total compliance to MIL-STD 883, contact
your local sales oirtce for the DAC8841BW/883 data sheet,
Table I. Serial Input Decode Table
- FIRST
|LSBDO‘ DILDZ ins I D4 I D5 I D6 ‘MSBD'IlLSBAOl A1 I A2 IMSBAS’
REV. A
ADDRESS
MSB LSB
-l, A3 I A2 1 Ali 0 DAC Updated
0 o 0 0 No Operation
0 o o 1 DAC A
o o 1 o DAC B
o o I 1 DAC C
o 1 o o DAC D
o 1 o 1 DAC E
o 1 1 o DAC F
o 1 1 1 DAC G
1 o o o DAC H
l 0 . 0 I No Operation
1 l . l 1 NI, Operation
MSB LSB
DAC Output Voltage
D7 D6 D5 D4 D3 D2 DI DO VOUT = D/128 (VIN - VREFL) + VREFL
o o o o o o o o VREFL
o o o o o o o 1 1/128 (VIN - VREFL) + VREFL
o 1 1 1 1 1 1 1 127/128 (VIN - VREFL) + VREFL
I o 0 0 0 0 0 0 VIN (Preset Value)
1 o o o o o o 1 129/128 (VIN - VREFL) q VREFL
1 1 1 1 1 1 1 0 254/128 (VIN - VREFL) + VREFL
1 1 1 1 1 1 1 255/128 (VIN - VREFL) + VREFL
Table II. Logic Control Input Truth Table
SDI CLK LD PTt Input Shift Register Operation
X L L H No Operation
X L H Shift One Bit In from SDI (Pin 20),
Shift One Bit* Out from SDO (Pin 18)
X X L L All DAC Registers = 8th,
X L H. H Load Serial Register Data into
DAC(X) Register
*Data shifted into the SDI pin appears twelve clocks later at the SDO pin.
