DAC8840-GBC ,8-Bit Octal, 4-Quadrant Multiplying, CMOS TrimDACSpecifications Apply for DACs A, B, C, D, E, F, G, H
Resolution N 8 Bits
Integral Nonlinearity IN ..
DAC8841FP ,8-Bit Octal, 2-Quadrant Multiplying, CMOS TrimDACSPECIFICATIONS
Input Clock Pulse Width tera, ter, 80 ns
Data Setup Time tos 40 ns
Data Hold Time ..
DAC8841FS ,0.3-7.0V; octal 8-bit, 2-quadrant multiplying, CMOS trimDAC. For dynamic level adjustment, trimmer replacementSpecifications Apply for DACs A, B, C,
D, E, F, G, H
Resolution N 8 Bits
Integral Nonlinearity I ..
DAC8841-GBC ,0.3-7.0V; octal 8-bit, 2-quadrant multiplying, CMOS trimDAC. For dynamic level adjustment, trimmer replacementSPECIFICATIONS
Input Clock Pulse Width tera, ter, 80 ns
Data Setup Time tos 40 ns
Data Hold Time ..
DAC8871SBPW ,16-Bit Single Channel, Serial Interface, +/-18V (High Voltage Bipolar) Output DAC 16-TSSOP -40 to 105features a• 16-Pin TSSOP Packagestandard high-speed clock (up to 50MHz), and a 3V• Selectable Reset ..
DAC8871SBPW ,16-Bit Single Channel, Serial Interface, +/-18V (High Voltage Bipolar) Output DAC 16-TSSOP -40 to 105This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
DM7407MX , Hex Buffer/Driver with High-Voltage Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains six independent gates each of wh ..
DM7407N ,Hex Buffers with High Voltage Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains six independent gates each of wh ..
DM7408N ,Quad 2-Input AND GatesFeaturesYAlternate Military/Aerospace device (5408) is available.This device contains four independ ..
DM7408N ,Quad 2-Input AND GatesGeneral DescriptionThis device contains four independent gates each of whichperforms the logic AND ..
DM7409N ,Quad 2-Input AND Gates with Open-Collector Outputs5409/DM7409Quad2-InputANDGateswithOpen-CollectorOutputsJune19895409/DM7409Quad2-InputANDGateswithOp ..
DM7410N ,Triple 3-Input NAND GatesFeaturesYAlternate Military/Aerospace device (5410) is available.Thisdevicecontainsthreeindependent ..
DAC8840FP-DAC8840FS-DAC8840-GBC
8-Bit Octal, 4-Quadrant Multiplying, CMOS TrimDAC
Diy ANALOG
DEVICES
8-Bit, Octal, 4-Guadrant
Multiplying, CMOS TrimDAC
DABBB40
FEATURES
Replaces 8 Potentiometers
1 MHz 4-Ouadrant Multiplying Bandwidth
No Signal Inversion
Low Zero Output Error
Eight Individual Channels
3-Wire Serial Input
500 kHz Update Data Loading Rate
:3 Volt Output Swing
Midscale Preset, Zero Volts Out
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Dynamic Level Adjustment
Special Waveform Generation and Modulation
GENERAL DESCRIPTION T
The DAC-8840 provides eight general purpose digitally con-
trolled voltage adjustment devices. The TrimDACY capability
allows replacement of the mechanical trimmer function in new
designs. The DAC-8840 is ideal for ac or dc gain control of up
to 1 MHz bandwidth signals. The 4-quadrant multiplying capa-
bility is useful for: signal inversion and modulation often found
in video convergence circuitry.
Internally the DAC-8840 contains eight voltage output CMOS
digital-to-analog converters, each with separate reference inputs.
Each DAC has its own DAC register which holds its output
state. These DAC registers are updated from an internal serial-
to-parallel shift register which is loaded from a standard 3-wire
serial input digital interface. Twelve data bits make up the data
word clocked into the serial input register. This data word is
decoded where the first 4 bits determine the address of the DAC
register to be loaded with the last 8 bits of data. A serial data
output pin at the opposite end of the serial register allows sim-
ple daisy-chaining in multiple DAC applications without addi-
tional external decoding logic.
TrimDAC is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accu rate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DECODED
ADDRESS
LOAD o- LOGIC
DATA DAC
4/ er REGISTER
SERIAL
SDI tr- ,’ DAC H VOUT H
REGISTER
A 'i'''''
GLK L DAC-8840
GND Vss soo PRESET
The DAC-884O consumes only 190 mW from ue5 V power sup-
plies. For single 5 V supply applications consult the DAC-8841.
The DAC-8840 is available in 24-pin plastic DIP, cerdip, and
SOIC-24 packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Tel: 617/329-4700 Fax: 617/326-8703
West Coast Central Atlantic
714/641-9391 214/231-5094 215/643-7790
MC884il---SPEClFlChTl0lG
(h, = +5 ll, Ilss = -5 ll, All VINX = +3 ll, IA = --4lr'0 to +85% apply
for 1llit-884tlF, unless otherwise noted)
Parameter Symbol Conditions I Min Typ Max Units
STATIC ACCURACY All Specifications Apply for DACs A, B, C, D, E, F, G, H
Resolution N 8 Bits
Integral Nonlinearity IN L tl/4 t l LSB
Differential Nonlinearity DNL All Devices Monotonic tl LSB
Output Offset VBZE E = 0, Sets D = 80H 25 mV
Output Offset Drift TCVBZ PR = 0, Sets D = 80H 10 wVf'C
REFERENCE INPUTS Applies to All Inputs VINX
Voltage Range WR Note 1 13 V
Input Resistance RIN D - 2BH, Code Dependent 3 6 kfl
Input Capacitance Cm D = F F,,, Code Dependent 19 30 pF
DAC OUTPUTS Applies to All Outputs VOUTX
Voltage Range OVR RL = 10 k0 :3 V
Output Current [OUT AVov-r <1 LSB I 5 i 10 mA
Capacitive Load Cr, No Oscillation 200 pF
DYNAMIC PERFORMANCE Applies to All DACs
Multiplying Gain Bandwidth GBW VINX = 100 mV p-p l 2.5 MHz
Slew Rate Measured 10% to 90%
Positive SR 1 AVOUTX= +6 V 1 3 4.0 V/ps
Negative SR- AVUUTX = -6 V l 3 2.5 V/ws
Total Harmonic Distortion THD VINX = 4 V p-p, D = FFH, 0.01 %
f = 1 kHz, fra, = 80 kHz
Spot Noise Voltage es f = 1 kHz 0.17 uV/VE
Output Settling Time ts tl LSB Error Band, D - 0 to FF,, 3.5 6 us
Channel-to-Channel Crosstalk G Measured Between Adjacent Channels,
f = 100 kHz 60 80 dB
Digital Feedthrough Q VINX = 0 V, D = 0 to 25510 6 nVs
POWER SUPPLIES
Power Supply Current loo W = 0 V 19 26 mA
Negative Supply Current Iss FK = 0 V 19 26 mA
Power Dissipation PDISS 190 260 mW
DC Power Supply Rejection Ratio PSRR W = 0 V, AVDD = :5% 0.0002 0.01 %/%
Power Supply Range PSR VDD, lvssl 4.75 5.00 5.25 V
DIGITAL INPUTS
Logic High Va, 2.4 V
Logic Low VIL 0.8 V
Input Current IL t10 "
Input Capacitance Cu. 7 10 pF
Input Coding Offset Binary
DIGITAL OUTPUT
Logic High Vor, IOH = -0.4 mA 3.5 V
Logic Low Vor., lor, = 1.6 mA 0.4 V
NOTE -
lMaximum input voltage is always 2 V less than VDD.
Specifications subject to change without notice.
(h, = +5 ll, Ilss = -5 ll, All VINX = +3 ll, T, = .-4tr't
TIMING SPECIFICATIONS to +85% apply for illit-884ilF, unless otherwise noted)
Parameter Symbol Min Max Units
Input Clock Pulse Width tcu, tCL 80 ns
Data Setup Time tras 40 ns
Data Hold Time tvu 20 ns
CLK to SDO Propagation Delay teo 120 ns
DAC Register Load Pulse Width tru, 70 ns
Preset Pulse Width [m 50 ns
Clock Edge to Load Time tesa.D 30 ns
Load Edge to Next Clock Edge trmcs 60 ns
-2- REV. A
DA88840
WAFER TEST LIMITS: (hm .r= +5 ll, Ilss = -5 ll, All llmlt = +3 ll, T, = +25°c, unless otherwise noted.)
DAC884OGBC
Parameter Symbol Conditions Limits Units
Integral Nonlinearity INL tl LSB max
Differential Nonlinearity DNL All Devices Monotonic tl LSB max
Output Offset VBZE W = 0, Sets D = 80H 25 mV max
Input Resistance (VINX) RIN D = 2Brr; Code Dependent 3 kft min
DAC Output Voltage Range OVR RL. = 10 kfl t3 V min
DAC Output Current lov, AVOUT < 1 LSB f :5 mA min
Slew Rate Measured 10% to 90%
Positive SR+ AVOUTX = +6 V 1.3 V/ws min
Negative SR-- AVOUTX -- -6 V 1.3 V/ws min
Positive Supply Current IDD Pk - 0 V 26 mA max
Negative Supply Current Iss Wt = 0 V 26 mA max
DC Power Supply Rejection Ratio PSRR tm = 0 V, AVDD = i5% 0.01 %/% max
Logic Input High Vm 2.4 V min
Logic Input Low V11. 0.8 V max
Logic Input Current IL :10 " max
Logic Output High Voss Iosa = -O.4 mA 3.5 V min
Logic Output Low Vor, lor, = 1.6 mA 0.4 V max
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guar
anteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
SDI t',D(A3)(A2)r(AsxAoy(or))tmsxDs)y(D4)r(ro3)(oz)r(m)rom)r(
CLK _/N/N/N/N/N/N/N/N/N/N/N/N,
DAC REGISTER LOAD A
.D; /'\
OUT 0V
DETAIL SERIAL DATA INPUT TIMING (Ea . -1")
(DATA IN) o X Ax or Dx X
ttas --.- - - tor,
(DATAOUT) o X _ X
tCH_> - tpp
1 '_-'''-,'
CLK N / \ l
V0 5 crcl LSB
0V " LSB ERROR BAND
PRESET TIMING
I xl LSB
:1 LSB ERROR BAND
Figure f, Timing Diagram
REV. A -3-
0A08840
PIN DESCRIPTION
PIN MNEMONIC DESCRIPTION
1 VOUTC DAC C Output
2 VomB DAC B Output
3 VomA DAC A Output
4 VINB DAC B Reference Input
5 VINA DAC A Reference Input
6 GND Ground
7 PT Preset Input, Active Low,
All DAC Registers = 8%
8 VINE DAC E Reference Input
9 VmF DAC F Reference Input
10 VOUTE me E Output
11 VomF DAC F Output
12 VOUT DAC G Output
13 VOUTH DAC H Output
14 VING DAC G Reference Input
15 VINH DAC H Reference Input
16 LD Load DAC Register Strobe, Active High Input
That Transfers the Data Bits from the
Serial Input Register into the Decoded
DAC Register. See Table l.
17 CLK Serial Clock Input, Positive Edge Triggered
18 SDO Serial Data Output, Active Totem Pole Output
19 Vss Negative 5 V Power Supply
20 SDI Serial Data Input
21 Vor, Positive 5 V Power Supply
22 V,ND DAC D Reference lnput
23 VIN DAC C Reference Input
24 VOUTD DAC D Output
ABSOLUTE MAXIMUM RATINGS
cr, = +25''C, unless otherwise noted)
Vor, to GND ........................ -().3, +7 v
Vss to GND ......................... +0.3, -7 V
me to GND ......................... VDD, Vss
VOUTX to GND ........................ Voo, Vss
Short Circuit IOUTX to GND ............... Continuous
Digital Input & Output Voltage to GND ........ VDD, Vss
Operating Temperature Range
Extended Industrial: DAC8840F ........ -4(YC to +85°C
Maximum Junction Temperature (T, max) ........ + 150°C
Storage Temperature ................ -65''C to + 150°C
Lead Temperature (Soldering, 10 sec) ........... +300''C
Package Power Dissipation ........... (T, Max -TA)/(hA
Thermal Resistance 8rs
Cerdip ............................... 64°C/W
P-DIP .............................. 57°C/W
SOIC-24 ............................. 70°C/W
ORDERING GUIDE
T emperature Package Package
Model Range Description Option
DAC8840FP -40T to --85oC Plastic DIP N-24
DAC8840FW -400C to +85°C Cerdip Q-24
DAC8840FS -40oC, to +85°C SOL-24 R-24
DAC8840GBC 1 25°C DICE
CAUTION
PIN CONFIGURATION
vourC l: . \J E] VOUTD
VOUTB E El VIN C
VOUTA E El VIN D
VIN B E DAC-8840 E vDD
V‘NA E (N23fovslige) El SDI
GND E El Vss
E E E] soo
Vm E E E] CLK
va E El LD
VOUTE E El VIN H
VourF E El VIN G
VouTG E El vourH
DICE CHARACTERISTICS
DIE SIZE 0.117 X 0.185 inch, 21,645 sq. mils
(2.9718 K 4.699 mm, 13.964 sq. mm)
The die backside is electrically common to FL,.
The DAC8840 contains 3236 transistors.
Il 'is 'l I.. o
o o o 8 z
> > > ' >
u. ca a 0 =2
i,' 8 3 J 7
'BOTH GND PADS (tht, 6b) ARE
BONDED TO PIN 6 OF PACKAGE.
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.
ESD SENSITIVE DEVICE
REV. A
Typical Performance Charaheristityr--oMMil
+112 DACs A, B, c, D SUPERIMPOSED
, 1/2 Ta = +25°c
g VDD = +5V
f, vss = -6V
t .V'NX.= "','
x W2 DACs E, F, G, H SUPERIMPOSED
.-1 fit
0 64 128 192 256
DIGITAL INPUT CODE - Decimal
Figure 2. Linearity Error
vs. Digital Input Code
INPUT RESISTANCE
100 soup/l-N-iv
'IN 'IN
'IN - REFERENCE INPUT CURRENT - pA
o 32 64 96 128 160 192 224 256
DIGITAL INPUT CODE - Decimal
Figure 5. Input Resistance vs. Code
0 -10 g
-45 CODE = ALL ON -20 J.
-90 -30 ‘5
435 -40
CODE = ALL ZEROS
PHASE - Degrees
10k 100k 1M 10M
FREQUENCY - Hz
Figure 8. Gain and Phase vs. Fre-
quency (Digital Input = 0 or 255m)
REV. A
TA-- +125 “c
TA = 025 "C
TA = -55 "C
LINEARITY ERROR — LSB
VDD= +5V
Vss=-6V
vIN x = +av
. 0 64 128 192 256
DIGITAL INPUT CODE - Decimal
Figure 3. Linearity Error vs. Digital
Code vs. Temperature
VIN = “H:
10 tu, ' 80kHz
tho RL=2kQ
TOTAL HARMONIC DISTORTION — %
10 100 " 10k 100k
FREQUENCY - Hz
Figure 6. Total Harmonic Distortion
vs. Frequency
INPUT C dB
OUTPUT D
CROSSTALK — dB
1k 10k 100k 1M 10M
FREQUENCY - Hz
Figure 9. DAC Crosstalk vs.
Frequency
vOUT HALF-SCALE — mV
V =+5V
-2.0 Vss ---w
-75 -50 -25 0 25 50 75 100 125
TEMPERATURE - "C
Figure 4. VOUT Half-Scale (80H)
vs. Temperature
VDD = +4.75v
vss = -4.75V
AVIN = 23V
vOUT _ SLEW HATE — V/pAs
".76 -60 -25 0 25 50 75
TEMPERATURE - 'C
100 125
Figure 7. VOUT Slew Rate vs.
Temperature
en — NOISE VOLTAGE ( _uV/
10 1k 10k 100k
FREQUENCY - Hz
Figure 10. Voltage Noise Density
vs. Frequency
