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DAC8802TIN/a100avai14-Bit, Dual Channel, Serial Interface, Multiplying Digital-to-Analog Converter
DAC8802IPWTIN/a5000avai14-Bit, Dual Channel, Serial Interface, Multiplying Digital-to-Analog Converter 16-TSSOP -40 to 85


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DAC8803IDBTG4 ,14-Bit, Quad Channel, Serial Interface, Multiplying Digital-to-Analog Converter 28-SSOP -40 to 85ELECTRICAL CHARACTERISTICSV = +2.7 V to +5.5 V; I X = Virtual GND, A X = 0 V, V A, B, C, D = 10 V, ..
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DAC8805QDBTR ,14-Bit, Dual Channel, Parallel Interface, Multiplying Digital-to-Analog Converter 38-TSSOP -40 to 125ELECTRICAL CHARACTERISTICSAll specifications at T = –40°C to +125°C, V = +2.7V to +5.5V, I = virtua ..
DAC8806IDB ,14-Bit, Single Channel, Parallel Interface, Multiplying Digital-to-Analog Converter 28-SSOP -40 to 85ELECTRICAL CHARACTERISTICSAll specifications at –40°C to +85°C, V = +2.7 V to +5.5 V, I = virtual G ..
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DAC8802-DAC8802IPW
14-Bit, Dual Channel, Serial Interface, Multiplying Digital-to-Analog Converter
DAC8802 DAC8802 www.ti.com SBAS351B–AUGUST 2005–REVISED FEBRUARY 2007 Dual, Serial Input 14-Bit Multiplying Digital-to-Analog Converter FEATURES DESCRIPTION • Relative Accuracy: 1 LSB Max The DAC8802 is a dual, 14-bit, current-output • Differential Nonlinearity: 1 LSB Max digital-to-analog converter (DAC) designed to operate from a single 2.7 V to 5.5 V supply. • 2-mA Full-Scale Current ±20%, with V = ±10 V The applied external reference input voltage V REF REF determines the full-scale output current. An internal • 0.5 μs Settling Time feedback resistor (R ) provides temperature FB • Midscale or Zero-Scale Reset tracking for the full-scale output when combined with • Separate 4Q Multiplying Reference Inputs an external I-to-V precision amplifier. • Reference Bandwidth: 10 MHz A doubled-buffered, serial data interface offers • Reference Dynamics: –105 dB THD high-speed, 3-wire, SPI and microcontroller compatible inputs using serial data in (SDI), clock • SPI™-Compatible 3-Wire Interface: (CLK), and a chip-select (CS). A common 50 MHz level-sensitive load DAC strobe (LDAC) input allows • Double Buffered Registers to Enable simultaneous update of all DAC outputs from Simultaneous Multichannel Update previously loaded input registers. Additionally, an • Internal Power-On Reset internal power-on reset forces the output voltage to zero at system turn-on. An MSB pin allows system • Industry-Standard Pin Configuration reset assertion (RS) to force all registers to zero code when MSB = 0, or to half-scale code when APPLICATIONS MSB = 1. • Automatic Test Equipment The DAC8802 is available in an TSSOP-16 package. • Instrumentation • Digitally Controlled Calibration V A B REF D0 D1 D2 R A FB D3 14 Input DAC A D4 I A DAC A OUT Register Register D5 R R D6 A A GND D7 D8 D9 D10 D11 R B D12 FB D13 Input DAC B A0 DAC B I B OUT SDI Register R Register R A1 A B GND CLK EN CS A DAC Power-On B Reset Decode DGND MSB LDAC RS Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2005–2007, Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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