DAC8420EP-DAC8420ES-DAC8420FP-DAC8420FS Fast Delivery |IC PHOENIX CO.,LIMITED

DAC8420ES ,Quad 12-Bit Serial Voltage Output DACCHARACTERISTICSPower Supply Sensitivity PSRR 0.002 0.01 %/%Positive Supply Current I 69 mADDNegativ ..
DAC8420FP ,Quad 12-Bit Serial Voltage Output DACCHARACTERISTICS(at V = +15.0 V 6 5%, V = –15.0 V 6 5%, V = +10.0 V,DD SS VREFHIV = –10.0 V, –408C ≤ ..
DAC8420FP ,Quad 12-Bit Serial Voltage Output DACfeatures unusually high circuitwith references of +2.5 V to ±10 V respectively. Power dissipa-densi ..
DAC8420FS ,Quad 12-Bit Serial Voltage Output DACFEATURESGuaranteed Monotonic Over TemperatureVREFHI VDDExcellent Matching Between DACs5 1Unipolar o ..
DAC8426FP ,Quad 8-Bit Voltage Out CMOS DAC Complete with Internal 10 V ReferenceGENERAL DESCRIPTIONlows the DAC8426’s analog and digital circuitry to be manufac-The DAC8426 is a c ..
DAC8426FS ,Quad 8-Bit Voltage Out CMOS DAC Complete with Internal 10 V ReferenceSPECIFICATIONS (V = +15 V 6 10%, AGND = DGND = 0 V, V = 0 V, T = –558C to +1258CDD SS Aapplies for ..
DM54LS191J ,Synchronous 4-Bit Up/Down Counters with Mode ControlFeaturesYhigh, it counts down. Counts 8-4-2-1 BCD or binaryYThese counters are fully programmable; ..
DM54LS240J ,Octal TRI-STATE Buffers/Line Drivers/Line ReceiversDM54LS240/DM74LS240,DM54LS241/DM74LS241OctalTRI-STATEBuffers/LineDrivers/LineReceiversApril1992DM54 ..
DM54LS240J/883 ,Octal TRI-STATE Buffer/Line Driver/Line Receiver (Inverting)DM54LS240/DM74LS240,DM54LS241/DM74LS241OctalTRI-STATEBuffers/LineDrivers/LineReceiversApril1992DM54 ..
DM54LS240J/883 ,Octal TRI-STATE Buffer/Line Driver/Line Receiver (Inverting)FeaturesYTypical power dissipation (enabled)YTRI-STATE outputs drive bus lines directlyInverting 13 ..
DM54LS245J ,TRI-STATE Octal Bus TransceiverFeatures YAlternate Military/Aerospace device (54LS245) is avail-YBi-Directional bus transceiver in ..
DM54LS251J ,TRI-STATE Data Selectors/MultiplexersFeaturesYTRI-STATE version of LS151These data selectors/multiplexers contain full on-chip bina-Yry ..

DAC8420EP-DAC8420ES-DAC8420FP-DAC8420FS
Quad 12-Bit Serial Voltage Output DAC
FUNCTIONAL BLOCK DIAGRAM
VOUTA
VOUTB
VOUTC
VOUTD
GNDCLSEL
VREFLOVSS
VREFHIVDD
SDI
CLK
CLR
REV.0Quad 12-Bit Serial
Voltage Output DAC
FEATURES
Guaranteed Monotonic Over Temperature
Excellent Matching Between DACs
Unipolar or Bipolar Operation
Buffered Voltage Outputs
High Speed Serial Digital Interface
Reset to Zero- or Center-Scale
Wide Supply Range, +5 V-Only to 615 V
Low Power Consumption (35 mW max)
Available in 16-Pin DIP and SOL Packages
APPLICATIONS
Software Controlled Calibration
Servo Controls
Process Control and Automation
ATE
The DAC8420 is available in 16-pin epoxy DIP, cerdip, and
wide-body SOL (small-outline surface mount) packages. Opera-
tion is specified with supplies ranging from +5 V-only to ±15 V,
with references of +2.5 V to ±10 V respectively. Power dissipa-
tion when operating from ±15 V supplies is less than 255 mW
(max), and only 35 mW (max) with a +5 V supply.
For applications requiring product meeting MIL-STD-883,
contact your local sales office for the DAC8420/883 data sheet,
which specifies operation over the –55°C to +125°C tempera-
ture range.
GENERAL DESCRIPTION
The DAC8420 is a quad, 12-bit voltage-output DAC with serial
digital interface, in a 16-pin package. Utilizing BiCMOS tech-
nology, this monolithic device features unusually high circuit
density and low power consumption. The simple, easy-to-use
serial digital input and fully buffered analog voltage outputs
require no external components to achieve specified performance.
The three-wire serial digital input is easily interfaced to micro-
processors running at 10 MHz rates, with minimal additional
circuitry. Each DAC is addressed individually by a 16-bit serial
word consisting of a 12-bit data word and an address header.
The user-programmable reset control CLR forces all four DAC
outputs to either zero or midscale, asynchronously overriding
the current DAC register values. The output voltage range, de-
termined by the inputs VREFHI and VREFLO, is set by the
user for positive or negative unipolar or bipolar signal swings
within the supplies allowing considerable design flexibility.
DAC8420–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(at VDD = +5.0 V 6 5%, VSS = 0.0 V, VVREFHI = +2.5 V, VVREFLD = 0.0 V, and
VSS = –5.0 V 6 5%, VVREFLO = –2.5 V, –408C ≤ TA ≤ +858C unless otherwise noted. See Note 1 for supply variations.)
MATCHING PERFORMANCE
AMPLIFIER CHARACTERISTICS
LOGIC CHARACTERISTICS
LOGIC TIMING CHARACTERISTICS
NOTESAll supplies can be varied ±5% and operation is guaranteed. Device is tested with VDD = +4.75 V.For single-supply operation (VVREFLO = 0 V, VSS = 0 V), due to internal offset errors INL and DNL are measured beginning at code 003H.Guaranteed but not tested.Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.VOUT swing between +2.5 V and –2.5 V with VDD = 5.0 V.All input control signals are specified with tr = tf =5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
ELECTRICAL CHARACTERISTICS
MATCHING PERFORMANCE
AMPLIFIER CHARACTERISTICS
SUPPLY CHARACTERISTICS
NOTESAll supplies can be varied ±5% and operation is guaranteed.Guaranteed but not tested.
DAC8420
(at VDD = +15.0 V 6 5%, VSS = –15.0 V 6 5%, VVREFHI = +10.0 V,
VVREFLO = –10.0 V, –408C ≤ TA ≤ +858C unless otherwise noted. See Note 1 for supply variations.)
DAC8420
WAFER TEST LIMITS
Logic Input Low Voltage
Logic Input Current
Positive Supply Current
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18.0 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –18.0 V
VSS to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +36.0 V
VSS to VVREFLO . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VSS – 2.0 V
VVREFHI to VVREFLO . . . . . . . . . . . . . . . . . . . +2.0 V, VDD – VSS
VVREFHI to VDD . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, +33.0 V
IVREFHI, IVREFLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Digital Input Voltage to GND . . . . . . . . . –0.3 V, VDD + 0.3 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Operating Temperature Range
EP, FP, ES, FS, EQ, FQ . . . . . . . . . . . . . . –40°C to +85°C
Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C
Thermal Resistance
Package TypeθJAθJCUnits
16-Pin Plastic DIP (P)70127°C/W
16-Pin Hermetic DIP (Q)8219°C/W
16-Lead Small Outline
Surface Mount (S)86222°C/W
NOTES
1θJA is specified for worst case mounting conditions, i.e., θJA is specified for
device in socket.
2θJA is specified for device on board.
CAUTIONStresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this
specification is not implied. Exposure to the above maximum
rating conditions for extended periods may affect device
reliability.Digital inputs and outputs are protected, however, permanent
damage may occur on unprotected units from high-energy
electrostatic fields. Keep units in conductive foam or packaging
3. Remove power before inserting or removing units from their
sockets.
4. Analog Outputs are protected from short circuits to ground
or either supply.
DICE CHARACTERISTICS
Die Size 0.119 × 0.283 inch, 33,677 sq. mils
(at VDD = +15.0 V, VSS = –15.0 V, VREFHI = +10.0 V, VREFLO = –10.0 V, TA = +258C
unless otherwise noted)
tCSH
tLD2
tCSS
tLD1
SDI
CLK
DATA LOAD SEQUENCE
tLDW
tCL
SDI
CLK
VOUT
DATA LOAD TIMING
tCLRW
±1LSB
CLSEL
CLR
VOUT
CLEAR TIMING
Timing Diagram1N4001
–10V
1N4001
+10V
1N4001
+15V1N4001
–15V
10kΩ
NC = NO CONNECT
Burn-In Diagram
ORDERING GUIDE
NOTESA complete /883 data sheet is available. For availability and burn-in informa-
tion, contact your local sales office.PMI division letter designator.Dice tested at +25°C only.
DAC8420
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTION
Power SuppliesVDD:Positive Supply, +5 V to +15 V.
VSS:Negative Supply, 0 V to –15 V.
GND:Digital Ground.
ClockCLK: System Serial Data Clock Input, TTL/CMOS levels. Data presented to the input SDI is shifted into
the internal serial-parallel input register on the rising edge of clock. This input is logically ORed with CS.
Control Inputs(All are CMOS/TTL compatible.)
CLR: Asynchronous Clear, active low. Sets internal data registers A-D to zero or midscale, depending on cur-
rent state of CLSEL. The data in the serial input shift register is unaffected by this control.
CLSEL: Determines action of CLR. If HIGH, a Clear command will set the internal DAC registers A-D to
midscale (800H). If LOW, the registers are set to zero (000H).
CS: Device Chip Select, active low. This input is logically ORed with the clock and disables the serial data
register input when HIGH. When LOW, data input clocking is enabled, see the Control Function Table.
LD: Asynchronous DAC Register Load Control, active low. The data currently contained in the serial input
shift register is shifted out to the DAC data registers on the falling edge of LD, independent of CS. Input data
must remain stable while LD is LOW.
Data Input(All are CMOS/TTL compatible.)
SDI: Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register, which
shifts data in beginning with DAC address Bit A1. This input is ignored when CS is HIGH.
The format of the 16-bit serial word is:
(FIRST) (LAST)
—Address Word— (MSB) —DAC Data Word— (LSB)
NC = Don’t Care.
Reference InputsVREFHI:Upper DAC ladder reference voltage input. Allowable range is (VDD – 2.5 V) to (VVREFLO +2.5 V).
VREFLO:Lower DAC ladder reference voltage input, equal to zero scale output. Allowable range is VSS to
(VVREFHI – 2.5 V).
Analog OutputsVOUTA through VOUTD:Four buffered DAC voltage outputs.
DIP
VDD
VOUTD
VOUTC
VREFLO
VREFHI
VOUTB
VOUTA
VSS
CLSEL
CLK
SDI
GND
CLR
NC = NO CONNECT
SOL
Table I.Control Function Logic Table
NC = Don’t Care.
NOTESCS and CLK are interchangeable.Returning CS HIGH while CLK is HIGH avoids an additional “false clock” of serial input data. See Note 1.Do not clock in serial data while LD is LOW.
OPERATION
Introduction
The DAC8420 is a quad, voltage-output 12-bit DAC with serial
digital input, capable of operating from a single +5 V supply.
The straightforward serial interface can be connected directly to
most popular microprocessors and microcontrollers, and can ac-
cept data at a 10 MHz clock rate when operating from ±15 V
supplies. A unique voltage reference structure assures maximum
utilization of DAC output resolution by allowing the user to set
the zero- and full-scale output levels within the supply rails. The
analog voltage outputs are fully buffered, and are capable of
driving a 2 kΩ load. Output glitch impulse during major code
transitions is a very low 64 nV-s (typ).
Digital Interface Operation
The serial input of the DAC-8420, consisting of CS, SDI, and
LD, is easily interfaced to a wide variety of microprocessor serial
ports. As shown in Table I and the Timing Diagram, while CS
is LOW the data presented to the input SDI is shifted into the
internal serial/parallel shift register on the rising edge of the
clock, with the address MSB first, data LSB last. The data for-
mat, shown above, is two bits of DAC address and two “don’t
care” fill bits, followed by the 12-bit DAC data word. Once all
16 bits of the serial data word have been input, the load control
LD is strobed and the word is parallel-shifted out onto the inter-
nal data bus. The two address bits are decoded and used to
route the 12-bit data word to the appropriate DAC data regis-
ter, see the Applications Information.
Correct Operation of CS and CLK
As mentioned in Table I, the control pins CLK and CS require
some attention during a data load cycle. Since these two inputs
are fed to the same logical “OR” gate, their operation is in fact
identical. The user must take care to operate them accordingly
in order to avoid clocking in false data bits. As shown in the
Timing Diagram, CLK must be either halted HIGH, or CS
brought HIGH during the last HIGH portion of the CLK fol-
lowing the rising edge which latched in the last data bit. Other-
wise, an additional rising edge is generated by CS rising while
CLK is LOW, causing CS to act as the clock and allowing a
false data bit into the serial input register. The same issue must
be considered in the beginning of the data load sequence also.
(000H) or midscale (800H), depending on the state of CLSEL as
shown in the Digital Function Table. The CLEAR function is
asynchronous and is totally independent of CS. When CLR
returns HIGH, the DAC outputs remain latched at the reset
value until LD is strobed, reloading the individual DAC data word
registers with either the data held in the serial input register prior
to the reset, or new data loaded through the serial interface.
Table II.DAC Address Word Decode Table
Programming the Analog Outputs
The unique differential reference structure of the DAC8420
allows the user to tailor the output voltage range precisely to the
needs of the application. Instead of spending DAC resolution
on an unused region near the positive or negative rail, the
DAC8420 allows the user to determine both the upper and
lower limits of the analog output voltage range. Thus, as shown
in Table III and Figure 1, the outputs of DACs A through D
range between VREFHI and VREFLO, within the limits speci-
fied in the Electrical Characteristics tables. Note also that
VREFHI must be greater than VREFLO.
1 LSB
VDD
VVREFHI
VVREFLO
DAC8420
Table III.Analog Output Code
FFF
7FF
Typical Performance Characteristics
VVREFHI – V
INL – LSB
Figure 4.INL vs. VREFHI (±15 V)
VVREFHI – V
DNL – LSB
Figure 2.Differential Linearity vs.
VREFHI (±15 V)
3.53.02.52.0VREFHI – V
DNL – LSB
Figure 3.Differential Linearity vs.
VREFHI (+5 V)
VVREFHI – V
INL – LSB
Figure 5.INL vs. VREFHI (+5 V)
T = HOURS OF OPERATION AT +125°C
FULL-SCALE ERROR WITH R
= 2k – LSB
CURVES NOT NORMALIZED
Figure 6.Full-Scale Error vs.
Time Accelerated by Burn-In
Figure 7.Zero-Scale Error vs.
Time Accelerated by Burn-In

Partno	Mfg	Dc	Qty	Available	Descript
DAC8420FS	ADI	N/a	4	avai	Quad 12-Bit Serial Voltage Output DAC
DAC8420EP	AD	N/a	66	avai	Quad 12-Bit Serial Voltage Output DAC
DAC8420ES	ADI	N/a	69	avai	Quad 12-Bit Serial Voltage Output DAC
DAC8420FP	AD	N/a	50	avai	Quad 12-Bit Serial Voltage Output DAC
DAC8420FP	BB	N/a	4	avai	Quad 12-Bit Serial Voltage Output DAC