DAC8408FPC ,Quad 8-Bit Multiplying CMOS D/A Converter with MemoryFEATURES A common 8-bit TTL/CMOS compatible input port is used toFour DACs in a 28 Pin, 0.6 Inch Wi ..
DAC8408FPC ,Quad 8-Bit Multiplying CMOS D/A Converter with MemoryCHARACTERISTICS (@ V = +5 V; V = 610 V; V A, B, C, D = 0 V; T = –558C to +1258C apply forDD REF OU ..
DAC8408FS ,Quad 8-Bit Multiplying CMOS D/A Converter with MemorySpecifications apply for DAC A, B, C, & D.) DAC8408Parameter Symbol Conditions Min Typ Max UnitsS ..
DAC8408FS. ,Quad 8-Bit Multiplying CMOS D/A Converter with MemorySpecifications apply for DAC A, B, C, & D.) DAC8408Parameter Symbol Conditions Min Typ Max UnitsS ..
DAC8408GP ,Quad 8-Bit Multiplying CMOS D/A Converter with MemorySpecifications subject to change without notice.–2–REV. ADAC8408@ V = +5 V; V = 610 V; V A, B, C, D ..
DAC8411IDCKT ,16bit, Single Channel, 80uA, 2.0V-5.5V DAC in SC70 Package 6-SC70 -40 to 125Features 3 DescriptionThe DAC8311 (14-bit) and DAC8411 (16-bit) devices1• Relative Accuracy:are low ..
DM54LS138J ,Decoders/DemultiplexersFeaturesused to minimize the effects of system decoding. WhenYDesigned specifically for high speed: ..
DM54LS151J ,Data Selector/Multiplexerfeatures complementary W and Y outputs. YTypical power dissipation 30 mWYAlternate Military/Aerospa ..
DM54LS154J ,4-Line to 16-Line Decoders/DemultiplexersDM54LS154/DM74LS1544-Lineto16-LineDecoders/DemultiplexersMay1989DM54LS154/DM74LS1544-Lineto16-LineD ..
DM54LS154J ,4-Line to 16-Line Decoders/DemultiplexersFeaturesYDecodes 4 binary-coded inputs into one of 16 mutuallyEach of these 4-line-to-16-line decod ..
DM54LS154J ,4-Line to 16-Line Decoders/DemultiplexersFeaturesYDecodes 4 binary-coded inputs into one of 16 mutuallyEach of these 4-line-to-16-line decod ..
DM54LS155J ,Dual 2-Line to 4-Line Decoders/Demultiplexers54LS155/DM54LS155/DM74LS155,54LS156/DM54LS156/DM74LS156Dual2-Lineto4-LineDecoders/DemultiplexersJun ..
DAC8408ET-DAC8408FP-DAC8408FPC-DAC8408FS-DAC8408FS.-DAC8408GP
Quad 8-Bit Multiplying CMOS D/A Converter with Memory
REV.A
Quad 8-Bit Multiplying CMOS
D/A Converter with MemoryA common 8-bit TTL/CMOS compatible input port is used to
load data into any of the four DAC data-latches. Control lines
DS1, DS2, and A/B determine which DAC will accept data.
Data loading is similar to that of a RAMs write cycle. Data can
be read back onto the same data bus with control line R/W. The
DAC8408 is bus compatible with most 8-bit microprocessors,
including the 6800, 8080, 8085, and Z80. The DAC8408 oper-
ates on a single +5 volt supply and dissipates less than 20 mW.
The DAC8408 is manufactured using PMI’s highly stable,
thin-film resistors on an advanced oxide-isolated, silicon-gate,
CMOS process. PMI’s improved latch-up resistant design elimi-
nates the need for external protective Schottky diodes.
ORDERING INFORMATION1NOTESBurn-in is available on commercial and industrial temperature range parts
in cerdip, plastic DIP, and TO-can packages. For outline information see Pack-
age Information section.For devices processed in total compliance to MIL-STD-883, add /883 after
part number. Consult factory for 883 data sheet.For availability and burn-in information on SO and PLCC packages, contact
your local sales office.
FEATURES
Four DACs in a 28 Pin, 0.6 Inch Wide DIP or 28-Pin JEDEC
Plastic Chip Carrier61/4 LSB Endpoint Linearity
Guaranteed Monotonic
DACs Matched to Within 1%
Microprocessor Compatible
Read/Write Capability (with Memory)
TTL/CMOS Compatible
Four-Quadrant Multiplication
Single-Supply Operation (+5 V)
Low Power Consumption
Latch-Up Resistant
Available In Die Form
APPLICATIONS
Voltage Set Points in Automatic Test Equipment
Systems Requiring Data Access for Self-Diagnostics
Industrial Automation
Multichannel Microprocessor-Controlled Systems
Digitally Controlled Op Amp Offset Adjustment
Process Control
Digital Attenuators
GENERAL DESCRIPTIONThe DAC8408 is a monolithic quad 8-bit multiplying digital-to-
analog CMOS converter. Each DAC has its own reference input,
feedback resistor, and onboard data latches that feature
read/write capability. The readback function serves as memory
for those systems requiring self-diagnostics.
FUNCTIONAL BLOCK DIAGRAM
DAC8408
DAC8408
ELECTRICAL CHARACTERISTICS(@ VDD = +5 V; VREF = 610 V; VOUTA, B, C, D = 0 V; TA = –558C to +1258C apply for
DAC8408AT/BT, TA = –408C to +858C apply for DAC8408ET/FT/FP/FPC/FS; TA = 08C to +708C apply for DAC8408GP, unless otherwise noted.
Specifications apply for DAC A, B, C, & D.)
DAC8408
@ VDD = +5 V; VREF = 610 V; VOUTA, B, C, D = 0 V; TA = –558C to +1258C apply for
DAC8408AT/BT, TA = –408C to +858C apply for DAC8408ET/FT/FP/FPC/FS; TA = 08C to +708C apply for DAC8408GP, unless otherwise noted.
Specifications apply for DAC A, B, C, & D. Continued
ELECTRICAL CHARACTERISTICSNOTESThis is an end-point linearity specification.Guaranteed to be monotonic over the full operating temperature range.ppm/°C of FSR (FSR = Full Scale Range = VREF-1 LSB.)Input Resistance Temperature Coefficient = +300ppm/°C.Logic Inputs are MOS gates. Typical input current at +25°C Is less than 10 nA.Guaranteed by design.From Digital Input to 90% of final analog output current.All Digital Inputs “0” or VDD.All Digital Inputs VIH or VIL.See Timing Diagram.Digital Inputs = 0 V to VDD or VDD to 0 V.Extrapolated: tS (1/2 LSB) = tPD + 6.2τ where τ = the measured first time con-
stant of the final RC decay.All Digital Inputs = 0 V; VREF = +10 V.
Specifications subject to change without notice.
*θJA is specified for worst case mounting conditions, i.e., θJA is specified for
device in socket for cerdip and P-DIP packages; θJA is specified for device
soldered to printed circuit board for SOL and PLCC packages.
CAUTIONDo not apply voltages higher than VDD +0.3 V or less than
–0.3 V potential on any terminal except VREF and RFB.The digital control inputs are diode-protected; however,
permanent damage may occur on unconnected inputs from
high energy electrostatic fields. Keep in conductive foam at
all times until ready to use.Use proper antistatic handling procedures.Absolute Maximum Ratings apply to both packaged devices
ABSOLUTE MAXIMUM RATINGS(TA = +25°C, unless otherwise noted.)
VDD to IOUT 2A, IOUT 2B, IOUT 2C, IOUT 2D . . . . . . . . . .0 V, +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, +7 V
IOUT 1A, IOUT 1B,
IOUT 1C, IOUT 1D to DGND . . . . . . . . .–0.3 V to VDD +0.3 V
RFBA, RFBB, RFBC, RFBD to IOUT . . . . . . . . . . . . . . . . .±25 V
IOUT 2A, IOUT 2B,
IOUT 2C, IOUT 2D to DGND . . . . . . . . .–0.3 V to VDD + 0.3 V
DB0 through DB7 to DGND . . . . . . . .–0.3 V to VDD + 0.3 V
Control Logic
Input Voltage to DGND . . . . . . . . . .–0.3 V + VDD + 0.3 V
VREFA, VREFB, VREFC, VREFD to
IOUT 2A, IOUT 2B, IOUT 2C, IOUT 2D . . . . . . . . . . . . . . . .±25 V
Operating Temperature Range
Commercial Grade (GP) . . . . . . . . . . . . . . . .0°C to +70°C
Industrial Grade (ET, FT, FP, FPC, FS) .–40°C to +85°C
Military Grade (AT, BT) . . . . . . . . . . . . . .–55°C to +125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
PIN CONNECTIONS
DAC8408
TOP VIEW
(Not to Scale)
DAC8408Burn-in Circuit
WARNING!
ESD SENSITIVE DEVICE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8408 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
DICE CHARACTERISTICSDIE SIZE 0.130 × 0.124 inch, 16,120 sq. mils
(3.30 × 3.15 mm, 10.4 sq. mm)
1. VDD15. DB6
2. VREFA16. DB7 (MSB)
3. RFBA17. A/B
4. IOUT 1A18. R/W
5. IOUT 2A/IOUT 2B19. DS1
6. IOUT 1B20. DS2
7. RFBB21. VREFD
8. VREFB22. RFBD
9. DB0 (LSB)23. IOUT 1D
10. DB124. IOUT 2C/IOUT 2D
11. DB225. IOUT 1C
12. DB326. RFBC
13. DB427. VREFC
14. DB528. DGND
WAFER TEST LIMITSat VDD = +5 V; VREF = 610 V; VOUTA, B, C, D = 0 V; TA = +258C, unless otherwise noted. Specifications apply for
DAC A, B, C, & D.NOTESThis is an endpoint linearity specification.FSR is Full Scale Range = VREF –1 LSB.Input Resistance Temperature Coefficient approximately equals +300 ppm/°C.Logic inputs are MOS gates.Typical input current at +25°C is less than 10 nA.All Digital Inputs are either “0” or VDD.All Digital Inputs are either VIH or VIL.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
DAC8408
TYPICAL PERFORMANCE CHARACTERISTICSSupply Current vs. Logic LevelAnalog Crosstalk vs. Frequency
Timing Diagram
AC FEEDTHROUGH ERRORThis is the error caused by capacitance coupling from VREF to
the DAC output with all switches off.
SETTLING TIMESettling Time is the time required for the output function of the
DAC to settle to within 1/2 LSB for a given digital input signal.
PROPAGATION DELAYThis is a measure of the internal delays of the DAC. It is defined
as the time from a digital input change to the analog output cur-
rent reaching 90% of its final value.
CHANNEL-TO-CHANNEL ISOLATIONThis is the portion of input signal that appears at the output of a
DAC from another DAC’s reference input. It is expressed as a
ratio in dB.
DIGITAL CROSSTALKDigital Crosstalk is the glitch energy transferred to the output of
one DAC due to a change in digital input code from other
DACs. It is specified in nVs.
PARAMETER DEFINITIONS
RESOLUTIONResolution is the number of states (2n) that the full-scale range
(FSR) of a DAC is divided (or resolved) into.
NONLINEARITYNonlinearity (Relative Accuracy) is a measure of the maximum
deviation from a straight line passing through the end-points of
the DAC transfer function. It is measured after adjusting for
ideal zero and full-scale and is expressed in LSB, %, or ppm of
full-scale range.
DIFFERENTIAL NONLINEARITYDifferential Nonlinearity is the worst case deviation of any adja-
cent analog outputs from the ideal 1 LSB step size. A specified
differential nonlinearity of ±1 LSB maximum over the operating
temperature range ensures monotonicity.
GAIN ERRORGain Error (full-scale error) is a measure of the output error be-
tween the ideal and actual DAC output. The ideal full-scale
output is VREF –1 LSB.
OUTPUT CAPACITANCEOutput Capacitance is that capacitance between IOUT 1A, IOUT 1B,
IOUT 1C, or IOUT 1D and AGND.
DAC8408
CIRCUIT INFORMATIONThe DAC8408 combines four identical 8-bit CMOS DACs
onto a single monolithic chip. Each DAC has its own reference
input, feedback resistor, and on-board data latches. It also fea-
tures a read/write function that serves as an accessible memory
location for digital-input data words. The DAC’s three-state
readback drivers place the data word back onto the data bus.
D/A CONVERTER SECTIONEach DAC contains a highly stable, silicon-chromium, thin-film,
R-2R resistor ladder network and eight pairs of current steering
switches. These switches are in series with each ladder resistor
and are single-pole, double-throw NMOS transistors; the gates
of these transistors are controlled by CMOS inverters. Figure 1
shows a simplified circuit of the R-2R resistor ladder section,
and Figure 2 shows an approximate equivalent switch circuit.
The current through each resistor leg is switched between IOUT 1
and IOUT 2. This maintains a constant current in each leg, re-
gardless of the digital input logic states.
Each transistor switch has a finite “ON” resistance that can in-
troduce errors to the DAC’s specified performance. These resis-
tances must be accounted for by making the voltage drop across
each transistor equal to each other. This is done by binarily-
scaling the transistor’s “ON” resistance from the most signifi-
cant bit (MSB) to the least significant bit (LSB). With 10 volts
applied at the reference input, the current through the MSB
switch is 0.5 mA, the next bit is 0.25 mA, etc.; this maintains a
constant 10 mV drop across each switch and the converter’s ac-
curacy is maintained. It also results in a constant resistance ap-
pearing at the DAC’s reference input terminal; this allows the
DAC to be driven by a voltage or current source, ac or dc of
positive or negative polarity.
Shown in Figure 3 is an equivalent output circuit for DAC A.
The circuit is shown with all digital inputs high. The leakage
current source is the combination of surface and junction leak-
ages to the substrate. The 1/256 current source represents the
constant 1-bit current drain through the ladder terminating re-
sistor. The situation is reversed with all digital inputs low, as
shown in Figure 4. The output capacitance is code dependent,
and therefore, is modulated between the low and high values.
Figure 1. Simplified D/A Circuit of DAC8408
Figure 2. N-Channel Current Steering Switch
Figure 3. Equivalent DAC Circuit (AII Digital Inputs HIGH)
