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DAC8248HP-DAC8248HS
Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter
REV.B
Dual 12-Bit (8-Bit Byte)
Double-Buffered CMOS D/A Converter
FEATURES
Two Matched 12-Bit DACs on One Chip
12-Bit Resolution with an 8-Bit Data Bus
Direct Interface with 8-Bit Microprocessors
Double-Buffered Digital Inputs
RESET to Zero Pin
12-Bit Endpoint Linearity (61/2 LSB) Over Temperature15 V to 115 V Single Supply Operation
Latch-Up Resistant
Improved ESD Resistance
Packaged in a Narrow 0.3" 24-Pin DIP and 0.3" 24-Pin
SOL Package
Available in Die Form
APPLICATIONS
Multichannel Microprocessor-Controlled Systems
Robotics/Process Control/Automation
Automatic Test Equipment
Programmable Attenuator, Power Supplies, Window
Comparators
Instrumentation Equipment
Battery Operated Equipment
GENERAL DESCRIPTIONThe DAC8248 is a dual 12-bit, double-buffered, CMOS digital-
to-analog converter. It has an 8-bit wide input data port that inter-
faces directly with 8-bit microprocessors. It loads a 12-bit word in
two bytes using a single control; it can accept either a least signifi-
cant byte or most significant byte first. For designs with a 12-bit or
16-bit wide data path, choose the DAC8222 or DAC8221.
The DAC8248’s double-buffered digital inputs allow both
DAC’s analog output to be updated simultaneously. This is par-
ticularly useful in multiple DAC systems where a common
LDAC signal updates all DACs at the same time. A single
RESET pin resets both outputs to zero.
The DAC8248’s monolithic construction offers excellent DAC-
to-DAC matching and tracking over the full operating tempera-
ture range. The DAC consists of two thin-film R-2R resistor
ladder networks, two 12-bit, two 8-bit, and two 4-bit data regis-
ters, and control logic circuitry. Separate reference input and
feedback resistors are provided for each DAC. The DAC8248
(continued on page 4)
FUNCTIONAL BLOCK DIAGRAM
PIN CONNECTIONS
24-Pin 0.3" Cerdip (W Suffix),
24-Pin Epoxy DIP (P Suffix),
24-Pin SOL (S Suffix)
DAC8248–SPECIFICATIONS
ELECTRICAL CHARACTERlSTICS(@ VDD = +5 V or +15 V; VREF A = VREF B = +10 V; VOUTA = VOUT B = 0 V; AGND = DGND = 0 V;
TA = Full Temp Range specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.)
NOTESMeasured using internal RFB A and RFB B. Both DAC digital inputs = 1111 1111 1111.Guaranteed and not tested.Gain TC is measured from +25°C to TMIN or from +25°C to TMAX.Absolute Temperature Coefficient is approximately +50 ppm/°C.From 50% of digital input to 90% of final analog output current. VREF A = VREF B = +10 V; OUT A, OUT B load = 100 Ω, CEXT = 13 pF.WR, LDAC = 0 V; DB0–DB7 = 0 V to VDD or VDD to 0 V.
17Settling time is measured from 50% of the digital input change to where the output settles within 1/2 LSB of full scale.See Timing Diagram.These limits apply for the commercial and industrial grade products.These limits also apply as typical values for VDD = +12 V with +5 V CMOS logic levels and TA = +25°C.
Specifications subject to change without notice.
Burn-In Circuit
DAC8248
DAC8248
ORDERING GUIDE1NOTESBurn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages.For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet.For availability and burn-in information on SO and PLCC packages, contact your local sales office.
(continued from page 1)
operates on a single supply from +5 V to +15 V, and it dissi-
pates less than 0.5 mW at +5 V (using zero or VDD logic levels).
The device is packaged in a space-saving 0.3", 24-pin DIP.
The DAC8248 is manufactured with PMI’s highly stable thin-
film resistors on an advanced oxide-isolated, silicon-gate,
CMOS technology. PMI’s improved latch-up resistant design
eliminates the need for external protective Schottky diodes.
ABSOLUTE MAXIMUM RATINGS(TA = +25°C, unless otherwise noted.)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, +17 V
AGND to DGND . . . . . . . . . . . . . . . . . .–0.3 V, VDD +0.3 V
Digital Input Voltage to DGND . . . . . . .–0.3 V, VDD +0.3 V
IOUT A, IOUT B to AGND . . . . . . . . . . . . . .–0.3 V, VDD +0.3 V
VREF A, VREF B to AGND . . . . . . . . . . . . . . . . . . . . . . . .±25 V
VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . . .±25 V
Operating Temperature Range
AW Version . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
EW, FW, FP Versions . . . . . . . . . . . . . . . .–40°C to +85°C
GP, HP, HS Versions . . . . . . . . . . . . . . . . . . .0°C to +70°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°C
NOTE
1uJA specified for worst case mounting conditions, i.e., uJA is specified for device in
socket for cerdip and P-DIP packages; uJA is specified for device soldered to printed
circuit board for SOL package.
CAUTIONDo not apply voltages higher than VDD or less than GND
potential on any terminal except VREF and RFB.The digital control inputs are Zener-protected; however,
permanent damage may occur on unprotected units from
high energy electrostatic fields. Keep units in conductive
foam at all times until ready to use.Do not insert this device into powered sockets; remove
power before insertion or removal.Use proper antistatic handling procedures.Devices can suffer permanent damage and/or reliability deg-
radation if stressed above the limits listed under Absolute
Maximum Ratings for extended periods. This is a stress rat-
ing only and functional operation at or above this specifica-
tion is not implied.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8248 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
11.AGND13.NC
12.IOUTA14.DB1
13.RFB A15.DB0(LSB)
14.VREF A16.RESET
15.DGND17.LSB/MSB
16.DB7(MSB)18.DAC A/DAC B
17.DB619.LDAC
18.DB520.WR
19.DB421.VDD
10.DB322.VREF B
11.DB223.RFB B
12.NC24.IOUT B
SUBSTRATE (DIE BACKSIDE) IS INTERNALLY
CONNECTED TO VDD.
DICE CHARACTERISTICS
WAFER TEST LIMITS@ VDD = +5 V or +15 V, VREF A = VREF B = +10 V, VOUT A = VOUT B = 0 V; AGND = DGND = 0 V; TA = 258C.NOTESMeasured using internal RFB A and RFB B.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
Die Size 0.124 × 0.132 inch, 16,368 sq. mils
(3.15 × 3.55 mm, 10.56 sq. mm)
DAC8248Channel-to-Channel Matching (DAC
A & B are Superimposed)
Nonlinearity vs. VREF
Nonlinearity vs. Code (DAC A & B
are Superimposed)
Differential Nonlinearity vs. VREF
Nonlinearity vs. VREF
Nonlinearity vs. Code at TA = –55°C,
+25°C, +125°C for DAC A & B
(All Superimposed)
Differential Nonlinearity vs. VREF
Nonlinearity vs. VDD
Absolute Gain Error Change vs. VREF
–Typical Performance Characteristics
Full-Scale Gain Error vs. TemperatureLogic Input Threshold Voltage
vs. Supply Voltage (VDD)
Supply Current vs. Temperature
Supply Current vs. Logic Input VoltageMultiplying Mode Frequency Response vs. Digital Code
Output Leakage Current vs. TemperatureAnalog Crosstalk vs. Frequency
DAC8248Four Cycle UpdateFive Cycle Update
Write Timing Cycle Diagram
PARAMETER DEFINITIONS
RESOLUTION (N)The resolution of a DAC is the number of states (2n) that the
full-scale range (FSR) is divided (or resolved) into; where n is
equal to the number of bits.
RELATIVE ACCURACY (INL)Relative accuracy, or integral nonlinearity, is the maximum de-
viation of the analog output (from the ideal) from a straight line
drawn between the end points. It is expressed in terms of least
significant bit (LSB), or as a percent of full scale.
DIFFERENTIAL NONLINEARITY (DNL)Differential nonlinearity is the worst case deviation of any adja-
cent analog output from the ideal 1 LSB step size. The devia-
tion of the actual “step size” from the ideal step size of 1 LSB is
called the differential nonlinearity error or DNL. DACs with
DNL greater than ±1 LSB may be nonmonotonic. ±1/2 LSB
INL guarantees monotonicity and ±1 LSB maximum DNL.
GAIN ERROR (GFSE)Gain error is the difference between the actual and the ideal
analog output range, expressed as a percent of full-scale or in
terms of LSB value. It is the deviation in slope of the DAC
transfer characteristic from ideal.
Refer to PMI 1990/91 Data Book, Section 11, for additional
digital-to-analog converter definitions.
GENERAL CIRCUIT DESCRIPTION
CONVERTER SECTIONThe DAC8248 incorporates two multiplying 12-bit current out-
put CMOS digital-to-analog converters on one monolithic chip.
It contains two highly stable thin-film R-2R resistor ladder net-
works, two 12-bit DAC registers, two 8-bit input registers, and
two 4-bit input registers. It also contains the DAC control logic
circuitry and 24 single-pole, double-throw NMOS transistor
current switches.
Figure 1 shows a simplified circuit for the R-2R ladder and tran-
sistor switches for a single DAC. R is typically 11 kΩ. The tran-
sistor switches are binarily scaled in size to maintain a constant
voltage drop across each switch. Figure 2 shows a single NMOS
transistor switch.
Figure 1.Simplified Single DAC Circuit Configuration.
(Switches Are Shown For All Digital Inputs at Zero)
