DAC8222FS ,Dual 12-Bit Double-Buffered Multiplying CMOS D/A ConverterSpecifications apply for DAC A and DAC B.)AParameter Symbol Conditions Min Typ Max UnitsSTATIC ACCU ..
DAC8228FP ,Dual 8-Bit CMOS D/A Converter with Voltage OutputCHARACTERISTICS at vDD = MW :5%, vREF = ov, v2 = +2.5v and Vor, = +15V 15%,VHEF Ir. ov, v, = +5v_
..
DAC8228FP ,Dual 8-Bit CMOS D/A Converter with Voltage Outputapplications requiring multiple D/A con-
verters without sacrificing circuit-board space. Reduced ..
DAC8228FS ,Dual 8-Bit CMOS D/A Converter with Voltage OutputAPPLICATIONS
. Disk Drive Systems V
. Automatic Test Equipment
. Process/lndustrial Contro ..
DAC8229 ,Dual 8-Bit, Voltage Output, Multiplying CMOS D/ACHARACTERISTICS at vDD = +11.4V or +15.75v;
ABSOLUTE MAXIMUM RATINGS fr, = +25°C, unless oth-
e ..
DAC8229FP ,Dual 8-Bit CMOS D/A Converter with Voltage OutputGENERAL DESCRIPTION
The DAC-8229 is a dual 8-bit, voltage output, multiplying CMOS
D/A converte ..
DM54LS04J ,Hex Inverting Gates54LS04/DM54LS04/DM74LS04HexInvertingGatesJune198954LS04/DM54LS04/DM74LS04HexInvertingGatesGeneralDe ..
DM54LS04J/883 ,Hex InverterGeneral DescriptionThis device contains six independent gates, each of which performs the logic INV ..
DM54LS08J ,Quad 2-Input AND GatesFeaturesYAlternate Military/Aerospace device (54LS08) is avail-This device contains four independen ..
DM54LS109AJ ,Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary OutputsFeaturesnotdirectlyrelatedtothetransitiontimeoftherisingedgeofYAlternate Military/Aerospace device ..
DM54LS10J ,Triple 3-Input NAND GatesFeaturesYAlternate Military/Aerospace device (54LS10) is avail-Thisdevicecontainsthreeindependentga ..
DM54LS10N ,Triple 3-Input NAND Gates54LS10/DM54LS10/DM74LS10Triple3-InputNANDGatesJune198954LS10/DM54LS10/DM74LS10Triple3-InputNANDGate ..
DAC8222FP-DAC8222FS
Dual 12-Bit Double-Buffered Multiplying CMOS D/A Converter
REV.C
Dual 12-Bit Double-Buffered
Multiplying CMOS D/A Converter
FEATURES
Two Matched 12-Bit DACs on One Chip
Direct Parallel Load of All 12 Bits for High Data
Throughput
Double-Buffered Digital Inputs
12-Bit Endpoint Linearity (�1/2 LSB) Over Temperature
+5 V to +15 V Single Supply Operation
DACs Matched to 1% Max
Four-Quadrant Multiplication
Improved ESD Resistance
Packaged in a Narrow 0.3" 24-Lead DIP and 0.3"
24- Lead SOL Package
Available in Die Form
APPLICATIONS
Automatic Test Equipment
Robotics/Process Control/Automation
Digital Gain/Attenuation Control
Ideal for Battery-Operated Equipment
GENERAL DESCRIPTIONThe DAC8222 is a dual 12-bit, double-buffered, CMOS digital-
to-analog converter. It has a 12-bit wide data port that allows a
12-bit word to be loaded directly. This achieves faster through-
put time in stand-alone systems or when interfacing to a 16-bit
processor. A common 12-bit input TTL/CMOS compatible
data port is used to load the 12-bit word into either of the two
DACs. This port, whose data loading is similar to that of a RAM’s
write cycle, interfaces directly with most 12-bit and 16-bit bus
systems. (See DAC8248 for a complete 8-bit data bus interface
product.) A common bus allows the DAC8222 to be packaged
in a narrow 24-lead 0.3" DIP and save PCB space.
The DAC is controlled with two signals, WR and LDAC. With
logic low at these inputs, the DAC registers become transparent.
This allows direct unbuffered data to flow directly to either
DAC output selected by DAC A/DAC B. Also, the DAC’s
FUNCTIONAL DIAGRAMdouble-buffered digital inputs will allow both DACs to be
simultaneously updated.
DAC8222’s monolithic construction offers excellent DAC-to-
DAC matching and tracking over the full operating tempera-
ture range. The chip consists of two thin-film R-2R resistor
ladder networks, four 12-bit registers, and DAC control logic
circuitry. The device has separate reference-input and feedback
resistors for each DAC and operates on a single supply from
+5 V to +15 V. Maximum power dissipation at +5 V using
zero or VDD logic levels is less than 0.5 mW.
The DAC8222 is manufactured with highly stable thin-film re-
sistors on an advanced oxide-isolated, silicon-gate, CMOS
technology. Improved latch-up resistant design eliminates the
need for external protective Schottky diodes.
DAC8222–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VDD = +5 V or +15 V, VREF A = VREF B = +10 V, VOUT A = VOUT B = 0 V; AGND = DGND = 0 V;
TA = Full Temperature Range Specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.)POWER SUPPLY
AC PERFORMANCE CHARACTERISTICS
SWITCHING CHARACTERISTICS
NOTESMeasured using internal RFB A and RFB B. Both DAC digital inputs = 1111 1111 1111.
16Settling time is measured from 50% of the digital input change to where the
output voltage settles within 1/2 LSB of full scale.
17Gain TC is measured from +25°C to TMIN or from +25°C to TMAX.
ABSOLUTE MAXIMUM RATINGS(TA = +25°C, unless otherwise noted.)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, +17 V
AGND to DGND . . . . . . . . . . . . . . . . . .–0.3 V, VDD +0.3 V
Digital Input Voltage to DGND . . . . . . .–0.3 V, VDD +0.3 V
IOUTA, IOUTB to AGND . . . . . . . . . . . . . .–0.3 V, VDD +0.3 V
VREFA, VREFB to AGND . . . . . . . . . . . . . . . . . . . . . . . . .±25 V
VRFBA, VRFBB to AGND . . . . . . . . . . . . . . . . . . . . . . . . .±25 V
Operating Temperature Range
AW Version . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
EW, FW, FP Versions . . . . . . . . . . . . . . . .–40°C to +85°C
GP, HP, HS Versions . . . . . . . . . . . . . . . . . . .0°C to +70°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°C
NOTEθJA is specified for worst-case mounting conditions, i.e., qJA is specified for
device in socket for Cerdip, and P-DIP packages; JA is specified for device
soldered to printed circuit board for SO package.
CAUTIONDo not apply voltages higher than VDD or less than GND
potential on any terminal except VREF and RFB.The digital control inputs are Zener-protected; however,
permanent damage may occur on unprotected units from
high-energy electrostatic fields. Keep units in conductive
foam at all times until ready to use.Do not insert this device into powered sockets; remove
power before insertion or removal.Use proper antistatic handling procedures.Devices can suffer permanent damage and/or reliability deg-
radation if stressed above the limits listed under Absolute
Maximum Ratings for extended periods.
PIN CONNECTIONS
24-Lead 0.3" Cerdip
24-Lead Plastic DIP
24-Lead SOL
28-Terminal LCC
NC = NO CONNECT
ORDERING GUIDE*Consult factory for DAC8222/883 MIL-STD data sheet.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
DAC822211.AGND13.DB4
12.IOUT A14.DB3
13.RFB A15.DB2
14.VREF A16.DB1
15.DGND17.DB0 (LSB)
16.DB11(MSB)18.DAC A/DAC B
17.DB1019.LDAC
18.DB920.WR
19.DB821.VDD
10.DB722.VREF B
11.DB623.RFB B
12.DB524.IOUT B
Substrate (die backside) is internally connected to VDD.
DICE CHARACTERISTICSDIE SIZE 0.124 × 0.132 inch, 16,368 sq. mils
(3.15 × 3.55 mm, 10.56 sq. mm)
WAFER TEST LIMITS(@ VDD = +5 V or +15 V, VREF A = VREF B = +10 V, VOUT A = VOUT B = 0 V; AGND = DGND = 0 V; TA = +25�C)Output Leakage
Input Resistance
Input Resistance Match
NOTESMeasured using internal RFB A and RFB B.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
Figure 1.Channel-to-Channel Match-
ing (DAC A and B are Superimposed)
Figure 4.Nonlinearity vs. VREF
Figure 7.Nonlinearity vs. Code
(DAC A and B are Superimposed)
TYPICAL PERFORMANCE CHARACTERISTICSFigure 2.Differential Nonlinearity
vs. VREF
Figure 5.Nonlinearity vs. VREF
Figure 8.Nonlinearity vs. Code at TA
= –55°C, +25°C, +125°C for DAC A and
B (All Superimposed)
Figure 3.Differential Nonlinearity
vs. VREF
Figure 6.Nonlinearity vs. VDD
Figure 9.Absolute Gain Error
Changes vs. VREF
DAC8222
TYPICAL PERFORMANCE CHARACTERISTICSFigure 10.Full-Scale Gain Error vs.
Temperature
Figure 15.Output Leakage Current
vs. Temperature
Figure 17.Interface Timing vs. VDD
Figure 11.Logic Input Threshold
Voltage vs. Supply Voltage (VDD)
Figure 12.Supply Current vs.
Temperature
Figure 16.Analog Crosstalk vs.
Frequency
Figure 13.Supply Current vs. Logic
Input Voltage
Figure 14.Multiplying Mode Frequency
Response vs. Digital Code
Figure 18.Burn-In Circuit
PARAMETER DEFINITIONS
RESOLUTION (n)The resolution of a DAC is the number of states (2n) into which
the full-scale range (FSR) is divided (or resolved); where n is
equal to the number of bits.
RELATIVE ACCURACY (INL)Relative accuracy, or integral nonlinearity, is the maximum de-
viation of the analog output (from the ideal) from a straight line
drawn between the end points. It is expressed in terms of least
significant bit (LSB), or as a percent of full scale.
DIFFERENTIAL NONLINEARITY (DNL)Differential nonlinearity is the worst case deviation of any adja-
cent analog output from the ideal 1 LSB step size. The devia-
tion of the actual “step size” from the ideal step size of 1 LSB is
called the differential nonlinearity error or DNL. DACs with
DNL greater than ±1 LSB may be nonmonotonic ±1/2 LSB
INL guarantees monotonicity and ±1 LSB maximum DNL.
GAIN ERROR (GFSE)Gain error is the difference between the actual and the ideal
analog output range, expressed as a percent of full-scale or in
terms of LSB value. It is the deviation in slope of the DAC
transfer characteristic from ideal.
See Orientation in Digital-to-Analog Converters Section of the
current data book, for additional parameter definitions.
GENERAL CIRCUIT DESCRIPTION
CONVERTER SECTIONThe DAC8222 contains four 12-bit registers (two input regis-
ters and two DAC registers), two highly stable thin-film R-2R
resistor ladder networks, and interface control logic circuitry.
Also included are 24 single-pole, double-throw, NMOS transis-
tor current switches.
Figure 19.Simplified Single DAC Circuit Configuration.
(Switches Are Shown for All Digital Inputs at Zero)
Figure 20.N-Channel Current Steering Switch
Figure 19 shows a simplified circuit for the R-2R ladder network
and transistor switches for one DAC. R is typically 11 kΩ. The
transistor switches are binarily scaled in size to maintain a con-
stant voltage drop across each switch. Figure 20 shows a single
NMOS transistor switch.
The binary-weighted currents are switched between IOUT and
AGND by the N-channel MOS transistor switches. The selec-
tion between IOUT and AGND is determined by the digital input
code. It is important to note here that the voltage difference
DAC8222between IOUT and AGND terminals be as close to zero as practi-
cal in order to keep DAC errors to a minimum. This is normally
done by connecting AGND to the noninverting input of an op
amp and IOUT to the inverting input. The DAC’s internal resis-
tor (RFB) can be used for the feedback resistor by connecting the
op amp’s output directly to the DAC’s RFB terminal. The op
amp also provides the current-to-voltage conversion for the
DAC’s output current. The output voltage is dependent on the
DAC’s digital input code and VREF, and is given by:
VOUT = –VREF × D/4096
where D is the digital input code integer number that is between
0 and 4095.
The DAC’s input resistance, VREF (Figure 19), is always equal
to a constant value, R. This means that VREF can be driven by a
reference voltage or current, ac or dc (positive or negative). It is
recommended that a low-temperature-coefficient external RFB
resistor be used if a current source is employed.
The DAC’s output capacitance (COUT) is code dependent and
varies from 90 pF (all digital inputs low) to 120 pF (all digital
inputs high).
Figure 19 shows a transistor switch in series with the R-2R lad-
der terminating resistor and RFB resistor. They were designed
into the DAC to binarily match the ladder leg switches and im-
prove power supply rejection and gain error temperature coeffi-
cient. The gates of these transistor switches are connected to
VDD, so that an “open-circuit” exists when VDD is not applied.
This means that an op amp’s output voltage will go to either
“rail” if powered up before the DAC. Also, RFB resistance can-
not be measured without VDD being applied.
Figure 21.Digital Input Structure For One Bit
DIGITAL SECTIONThe DAC8222’s digital inputs are CMOS inserters. They were
designed to convert TTL and CMOS input logic levels into
voltage levels to drive the internal circuitry. The digital inputs
are TTL compatible at VDD = +5 V and CMOS compatible at
VDD = +15 V. The DAC8222 can use +5 V CMOS logic levels
with VDD = +12 V; however, supply current will rise to approxi-
mately 5 mA–6 mA.
Figure 21 shows the DAC’s digital input register structure for
one bit. This circuit drives the DAC register. Digital controls φ
and φ shown are generated from DAC A/DAC B and WR con-
trol signals.
As shown in Figure 21, these inputs are electrostatic-discharge
protected with two internal distributed diodes; they are con-
nected between VDD and DGND. Each digital input has a typi-
cal input current of less than 1 nA.
When the digital inputs are in the region of +1.2 V to +2.8 V
(peaking at +1.8 V) using a +5 V power supply or in the region
of +1.7 V to +12 V (peaking at +3.9 V) with a +15 V power
supply, the input register transistors are operating in their linear
region and draw current from the power supply. It is therefore,
recommended that the digital input voltages be as close to the
supply rails (VDD and DGND) as is practically possible to keep
supply currents at a minimum. The DAC8222 may be operated
with any supply voltage between the range of +5 V to +15 V.
INTERFACE CONTROL LOGICThe DAC8222’s input control logic circuitry is shown in Figure
22. Note how the WR signal is used in conjunction with DAC
A/ DAC B to load data into either input register. LDAC loads
data from the input registers to the DAC register; the DAC’s
analog output voltage is determined by the data contained in
each DAC register.
The truth table for the DAC registers is shown in the Mode Se-
lection Table. Note how the input register is transparent when
WR is low and LDAC is high, and that the DAC register is
transparent when WR is high and LDAC is low (LDAC updates
the DAC’s analog output voltage). The DAC is transparent
from input to output when WR and LDAC are both low, and
the DAC is latched (input and output is not being updated)
when WR and LDAC are both high.
Figure 22.Input Control Logic
