DAC8221GP ,Dual 12-Bit Buffered Multiplying CMOS D/A ConverterCHARACTERISTICS at VDD = +5V or +15V, V
PACKAGE TYPE , A(NOTE 1) It: UNITS
24-Pin Hermetic DIP ..
DAC8221GP ,Dual 12-Bit Buffered Multiplying CMOS D/A ConverterSpecifications apply for DAC A and DAC B.
DAC-8221
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT ..
DAC8222FP ,Dual 12-Bit Double-Buffered Multiplying CMOS D/A ConverterSpecifications subject to change without notice.–2–REV. CDAC8222ABSOLUTE MAXIMUM RATINGSPIN CONNECT ..
DAC8222FS ,Dual 12-Bit Double-Buffered Multiplying CMOS D/A ConverterGENERAL DESCRIPTIONdouble-buffered digital inputs will allow both DACs to beThe DAC8222 is a dual 1 ..
DAC8222FS ,Dual 12-Bit Double-Buffered Multiplying CMOS D/A ConverterCHARACTERISTICS V = +5 V V = +15 VDD DD8 10–55°C to +125°C All Temps+25°C–40°C to +85°CDAC Sel ..
DAC8222FS ,Dual 12-Bit Double-Buffered Multiplying CMOS D/A ConverterSpecifications apply for DAC A and DAC B.)AParameter Symbol Conditions Min Typ Max UnitsSTATIC ACCU ..
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DM54LS00J ,Quad 2-Input NAND Gates54LS00/DM54LS00/DM74LS00Quad2-InputNANDGatesJune198954LS00/DM54LS00/DM74LS00Quad2-InputNANDGatesGen ..
DM54LS04J ,Hex Inverting Gates54LS04/DM54LS04/DM74LS04HexInvertingGatesJune198954LS04/DM54LS04/DM74LS04HexInvertingGatesGeneralDe ..
DM54LS04J/883 ,Hex InverterGeneral DescriptionThis device contains six independent gates, each of which performs the logic INV ..
DM54LS08J ,Quad 2-Input AND GatesFeaturesYAlternate Military/Aerospace device (54LS08) is avail-This device contains four independen ..
DAC8221EW-DAC8221FP-DAC8221GP
Dual 12-Bit Buffered Multiplying CMOS D/A Converter
ANALOG
DEVICES
Dual 12-Bit Buffered
Multiplying CMOS MI Converter
DACBZZI
FEATURES
. Two Matched 12-Bit DACs on One Chip
. Packaged in a Narrow 0.3" 24-Pin DIP
. Direct Parallel Load of All 12 Bits for High DataThroughput
. (ha-Chip Latches for Both DACs
. 12-Bit Endpont Linearity (:1/2 LSB) Over Temperature
. +5V to +15V Single Supply Operation
. DACs Matched to 0.2% Typically
. Four-Quadrant Multiplication
. Improved ESD Resistance
. Available in Die Form
APPLICATIONS
. Automatic Test Equipment
. lndustrialAutomation
. Robotics/Process Control
. Programmable Instrumentation Equipment
. Digital Gain/Attenuation Control
. Ideal for Battery-Operated Equipment
ORDERING INFORMATION'
PACKAGE
MILITARY' INDUSTRIAL COMMERCIAL
ERROR TEMPERATURE TEMPERATURE TEMPERATURE
RELATIVE GAIN
ACCURACY
(+ sv or +1 5V) -SS''C to +125°C -aty'C to +85°C 0''C to +70°C
21/2 LSB sl LSB DAC8221AW DAC8221EW -
21/2 LSB tit LSB - - DACB221GP
xl LSB x4 LSB - DAC8221FW DAC8221HP
xl LSB :4 LSB - DAC8221FP DAC8221H8tt
- For devices processed in total compliance to MlL-SDT-883. add /883 after part
number. Consult factory for 883 data sheet.
t Burn-in is available on commercial and industrial temperature range parts in
CerDIP, plastic DIP, and TO-can packages.
tt For availability and burn-in information on so and PLCC packages. contact
your local sales office.
GENERAL DESCRIPTION
The DAC-8221 combinestwoidentical12-bit,multiplying,digital-
to-analog converters into a single CMOS chip. This device is
electrically similar to DAC-8212 with improved microprocessor
interface timing and is packaged in a narrow 0.300" DI P. Mono-
lithic construction offers excellent DAC-to-DAC matching and
tracking over the full operating temperature range, The DAG-
8221 consists of two thin-film R-2R resistor-ladder networks,
two 12-bit data latches, one 12-bit input buffer, and control
logic. The DAC-8221 operates on a single supply from +5V to
+15V. Maximum power dissipation with 0V and +5V logic levels
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed byAnalog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
REV. B
and a +5V supply is less than 0.5mW. The DAC-8221 is manu-
factured using PMI's highly-stable, thin-film resistors on an
advanced oxide-isolated, silicon-gate, CMOS process. PMI's
improved latch-up resistant design eliminates the need for
external protective Schottky diodes.
Acc)mmon12-bit(TTL/CMOS compatible) input port is used to
load a 12-bit-wide word into either of the two DACs. This port,
whose data loading is similar to that of a RAM's write cycle,
interfaces directly with most 12-bit or wider bus systems. With
Wt and eg lines at logic LOW, the input data registers are trans-
parent. This allows direct unbuffered data to flow directly to the
DAC output selected by DAC A/DAC B control input. For
applications requiring double-buffering, see the DAC-8222.
PIN CONNECTIONS
AGND 'rr:],; Iou-ra
'DUTA 2 Earn: 24-PIN
RFB A E E VREFB 0.3" CERDIP
vnzn E E Van (W-Suffix)
DGND E E W
(MSB) 0311 E E ES M-PIN
Dam EPOXY DIP
E E DAC A/DAC B .
DB9 E E DB0 (L33) (P-Suffix)
Dan E E DBI
DB7 10 E DB2 24-PIN s_OL
Des 11 E DB3 (S-Suffix)
ass 12 E DBA
FUNCTIONAL DIAGRAM
DBO but A
DATA INPUT DAC
INPUTS BUFFER REGISTER
CONTROL
LOGIC iout a
REGISTER
VREF a
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106. U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 wa: 7t0t394-6677
Telex: 924491 Cable: ANALOG NORWOODMASS
DACBZZI
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted.)
VDD to AGND .............................................................. 0V, +17V
VDD to DGND ._...P...PPT...r...............q....q...P.F................... 0V, +17V
AGND to DGND ............................................. -th3V, VDD +0.3V
Digital Input Voltage to DGND ...................... --th3V, VDD +0.3V
lOUT A' lOUT B to AGND .................................. -0.3V, VDD +0.3V
REF A' REF B to AGND .................................................... A5V
RFB A' RFB B to AGND .................................................... s25V
Operating Temperature Range
AW Version ................................................. --55''C to +125°C
EW, FW, FP Versions ................................... -4ty'C to +85°C
GP, HP, HS Versions ...................................... -ty't) to +70°C
Junction Temperature ... ....... +150C
Storage Temperature ..................................... -65 C to +150°C
Lead Temperature (Soldering, 60 sec) ......................... +300°C
ELECTRICAL CHARACTERISTICS atVDD = +5V or +15V, V
PACKAGE TYPE ' (NOTE 1) le UNITS
24-Pin Hermetic DIP (W) 69 10 "CM
24-Pln Plastic DIP (P) 62 32 "C/W
24-Pin SOL (S) 72 24 "CIW
1.9 A is specified for worst case mounting conditions. i.e.. e A is specified for
evice in socket for CerDIP, and P-DIP packages; 6 is gpecified for device
soldered to printed circuit board for SOL package.
CAUTION:
l. Do no apply voltages higher than VDD Dr less than GND potential on any termi-
nal except VREF and Rrsr
2. The digital coniml inputs are atsnerpoteMtad; however. permanent damage
may occur on unprotected units from high-energy electrostatic fields. Keep
units in conductive foam at all times until ready to use.
3. Do not insert this device into powered sockets; remove power before insertion
or removal.
4. Use proper anti-static handling procedures.
. Stresses above those listed under "Absolute Maximum Ratings' may cause
permanent damage to the device. This is a stress rating only and functional
operation at or above this specification is not implied.
= vREF B = new vOUTA = Vou, B = OV; AGND = DGND = ov;
TA = Full Temp, Range specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.
DAC-8221
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY
Resolution N 12 - - Bits
. . . _ DAC-8221NEIG - :02 sl/2
Relative Accuracy INL Endpoint Linearity Error D A C- 8 2 2 1 B /F /H _ :04 sl LSB
Differential Nonlinearity DNL All Grades are Monolonic - sod sl LSB
DAC-8221A/E - :01 Al
F II S I G . E
”mo: 8 an rror GFSE DAC-8221G - 10.4 " LSB
DAC-8221B/F/H - Mrs "
Gain Temperature
Coefficient TCGFS (Notes 2. 7) - " " ppm/‘C
AGain/ATemperature
0:11pm :23 Current I All Digital Inputs = T,x = +25°c - tl :10 nA
OUT A . ' LKG 0000 0000 0000 TA = Full Temp. Range - " s50
IOUT B (Pin 24)
nput esistance RREF (Note 9) a 22 15 kn
(RREF A' RREF 3)
Input Resistance Match ARREF _ 102 sl %
(RREF ARREF s) RREF
DIGITAL INPUTS
v = +5V 2.4 - -
_ . . DD v
Digital Input High VINH VDD = +15V 13.5 _ _
V = +5V - - 0.8
' . DD v
Digital Input Low VINL Von = +15V - - 1.5
V = 0V or V T = +25°C - :0.006 tl
I IN DD A
nput Current Im and VINL or VINH TA = Full Temp. Range - 30.1 :10 WA
Input Capacitance C DB0 - DBII - - 10 pF
(Note 2) IN W), a. DAC A/DAC B - - 15
REV. B
M08221
ELECTRICAL CHARACTERISTICS at VDD = WN or +15V, V
REF B = +10V, V
=V0UTB
= 0V; AGND = DGND = 0V;
TA = Full Temp Range specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.
Continued
DAC-8221
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
All Digital Inputs VINL or VI NH - 1 2 mA
Supply Current '00 -
All Digital Inputs 0V or VDD - 2 100 WA
DC Power Supply
Rejection Ratio PSRR AVDD = 15% - - 0.002 %/%
(AGain/AVDD)
AC PERFORMANCE CHARACTERISTICS (Note 2)
Propagation Delay tt
(Notes 4, 5) 1pd TA - +25 C - - 350 ns
Current Settling Time
t T = 25''C - M 1 s
(Notes 5, 6) s A ' t) 5 "
Com A DAC Latches Loaded - 30 90
COUY B with 0000 0000 0000 - M 120
Output Capacitance pF
COUT A DAC Latches Loaded - 60 120
COUTB wi1h111111111111 - 30 90
V to I q V = 20V .
FT REF A OUT A' REF A " _ - -70
A = 1 . T = 0
AC Feedthrough at f 00kHa; A +25 C dB
I or I
A ' - '
OUT OUT B FT VHEF a to 'our 3, VREF a - 20Vp.p', - - -70
B f=100kHz;TA = +25°C
SWITCHING CHARACTERISTICS Vor, = +5V VDD = +151f
(Notes 2, 3) +25°c -40''C TO +8ti''C -55''C TO +1 25''C ALL TEMPS
(Note 8) (Note 10)
Chip Select to
Write Set-Up Time tcs 130 160 160 70 ns
Chip Select to
Write Hold Time to H 0 0 O o ns
DAC Select to
1 1 T MIN
Write Set-Up Time tAS 20 140 60 o ns
DAC Select to
Write Hold Time tAH O 0 o f) ns
Data Valid ta
t 1 21 22 90 MIN
Write Set-Up Time D s go o 0 ns
Data Valid to
Write Hold Time tor, o D 0 10 ns
Write Pulse Width tw R 140 180 170 90 ns MIN
NOTES:
1. Measured using internal RFB A and HFB a' Bath DAC digital inputs = 6. Settling time is measured from 50% of the digital input change to where the
1111 1111 1111. output voltage settles within 1/2 LSB of full scale.
2. Guaranteed and not tested. r. Gain TC is measured from +25°C to TMIN or from +25''C to TM Ax-
3. See timing diagram. 8. These limits apply for the commercial and industrial grade products.
4. From 50% of digital input to 90% of Mal analog ou1putcurrent. VREF A = 9. Absolute temperature Coefficient is approximately +50ppm/''C.
VREF B = new OUT A, OUT B load =1oon,cEXT =13pF.
.wa, cs = 0viDB0-DB11=tNttoVm:sorvnDto ov.
REV. B
. These limits also apply as typical values for VDD = +12V with +5V CMOS
logic levels and TA = +25°C.
DACBZZI
DICE CHARACTERISTICS
10 11 12
DIE SIZE 0.124 x 0.132 inch, 16,368 sq. mils
(3.15 x 3.35 mm, 10.55 sq. mm)
D811 (MSB)
DB0 (LSB)
93c A/DAC B
Vrwr a
'our B
Substrate (die backside) is internally connected to VDD.
WAFER TEST LIMITS at Voo-- +5V or +15V, VREFA= VREF B = +10V, VOUTA= VOUT B = 0V; AGND = DGND = 0V; TA: 25°C.
DAC-822IGBC
PARAMETER SYMBOL CONDITIONS LIMIT UNITS
Relative Accuracy lNL Endpoint Linearity Error tl LSB MAX
Differential Nonlinearity DNL All Grades are Guaranteed Monotonic t1 LSB MAX
Full Scale
I tall ts--111111111111 i4
Gain Error (Note 1) GFSE D gl a npu s LSB MAX
t tL k ' ' = 0 00
Cu pu ea age 'LKG Digital Inputs 0000 0000 0 :10 nA MAX
(IOUT A, IOUT s) Pads 2 and 24
Input Resistance anlN/
R Pads 4 and 22 8/15
(RREF A, RREF s) REF anAX
RREFA: RREFB Input ARREF +
Resistance Match REEF uFl % MAX
Digital input VDD = +5v 2.4
High V'NH VDD=+15V 13.5 V MIN
Digital Input va, = HN 0.8
Low INL VDD = +15V 1.5 MA
Digital Input
Current IIN vIN = OV or VDD; VNL or vINH tl " MAX
All Digital Inputs VINL or VINH 2
Supply current lruo All Digital Inputs OV or Vraro 0.1 mA MAX
DC Supply Rejection PSRR AVDD = :5% 0.002 %/% MAX
(hGain/aVoo)
NOTES:
1. Measured using internal RFBAand Egg B.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. E
DACBZZI
TYPICAL PERFORMANCE CHARACTERISTICS
NONLINEARIYY1LSB)
NONLINEAHITY (L55)
NONLINEAHITV (L89)
REV. B
-0 25 .
CHANNEL-TO-CHANNEL
MATCHING (DAC A & B
ARE SUPERIMPOSED)
vm, = +15v
VRSF = +1ov
Tn = +25°c
1024 2048 3072
DIGITAL INPUT CODE (DECIMAL)
NONLINEARITY
VS VREF
"cur-s-s-a-sr o 24 s 8
Vner (VOLTS)
NONLINEARITY vs CODE
(DAC A a B ARE
SUPERIMPOSED)
vm, -- usv
VREF=+10V
TA = are
DIGITAL INPUT CODE (DECIMAL)
DNL (LSB)
NONLINEARITV (LSE)
NONLINEARITV (LSB)
DIFFERENTIAL
NONLINEARITY
" VnEF
-10 " -6 " 2 t) 2 4 6 B 10
bsr (VOLTS)
NONLINEARITY
VS VREF
-10-8-6-4-2 o 2 4 e s
vmwoLTS)
NONLINEARITY vs CODE AT
TA = -55''C, +25°c,
+125°c FOR me A & B
(ALL SUPERIMPOSED)
1.00 T
vDD - +15v
0.75 -Vrer = +1ov
o e,etetttrt " i)1rest,itee V“.
1024 2048 3072 4096
DIGITAL INPUT CODE (DECIMAL)
DNL (LSB)
NONLINEARITV (L58)
GAIN ERROR (LSB)
DIFFERENTIAL
NONLINEARITY
VS VREF
-10 -3 -5 -4 2 0 p 4 6 8 10
VREFWOLTS)
NONLINEARITY
thii25
0 5 ttl 15
SUPPLY VOLTAGE (VOLTS)
ABSOLUTE GAIN ERROR
CHANGE VS VREF
VDD = l 15v
TA = ~25°c
.710787674 -2 o 2 4 6 e10
VREF(VOLTS)
0A88221
TYPICAL PERFORMANCE CHARACTERISTICS
LOGIC INPUT THRESHOLD
VOLTAGE " SUPPLY
VOLTAGE (VDD)
FULL-SCALE GAIN ERROR
vs TEMPERATURE
Van -- HSV vREF = mm
= +10V TA:+25°C
x 2 L1
lf, E o
a r- w
o E fl -
3 g 5 va _ 2.4if
g a vINL = o.sv
175 -50 -its 0 +25 +50 +75 +100 +125 0 5 to 15
TEMPERATURE CC) Ifoo (VOLTS)
SUPPLY CURRENT vs
LOGIC INPUT VOLTAGE
ALL BITS ON
TA = +25°c '
= +15v ‘f - DBN
>' F. Dee
1600 Von = -w E 9
it il , MN
l 1400 VDD = +12v >3 5 DB.
ru 1200 l g
2 g - DB2
l 1000 - 3
- z " LSB 030
E 800 g s t ,
' 600 o o
g 400 id L-
LI a m
k 200 a
il 1 l 3 4 s 6 7 8 9 " 11 12 13 T4
DIGITAL INPUT (VOLTS)
ANALOG CROSSTALK
" FREQUENCY
OUTPUT LEAKAGE CURRENT
vs TEMPERATURE
vDD =+15v
TA=+25°C
VIN AT VRIF B
Paur AT DAG A
VREFAGROUNDED
VOUT A/VREFB
Van: "w
VREF =_1DV
'LKG ~ OUTPUT LEAKAGE (M)
OUTPUT ATTENUATION (dB)
-15 -50 -96 n " so " um 125 " 10k 100k
TEMPERATURE CC) FREQUENCY (Hz)
ALL BITS OFF
SUPPLY CURRENT (mA)
SUPPLY CURRENT
vs TEMPERATURE
2.0 I I
VDD = +15v
Vx = -1.W
0.4 _---'''''
-75 -50 -25 o 25 50 75 100 125
TEMPERATURE CCI
MULTIPLYING MODE
FREQUENCY RESPONSE
vs DIGITAL CODE
FREQUENCY (Hz)
INTERFACE TIMING (nu)
ATTENUATION (d8)
1M 10M
INTERFACE TIMING
vs Von
k (van '' +sv TO UZV)
ht: ' 0 TO +sv
TA‘ +25'C
% = oro 'tsv-
(vm =usV)
l, _ A
"ii' ‘_r
As... g
s to 15 20
van (vows)
REV. E
DAC8221
BURN-IN CIRCUIT
+15V:o.5v
FTOVt0.5V C NV,
nocaximui
C" l A-
NOTES: 12
l. c1= c2 4.7pF TANTALUM, 50v DC; EVERY 10TH DEVICE.
2, c3: c4 0.01uF CERAMIC. 50V DC; EVERY 10TH DEVICE,
Ca = C2
l 1m I
DAC-8221 18 5kg _ R2
3. ALL MATERIAL TO WIYHSTAND1SODC.
WRITE CYCLE TIMING DIAGRAM
1(:54’ low
CHIP SELECT
---us-- ‘AM
DAC A/B
EMS - 0 tur,
NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES
MEASURED FROM 10% To 90% OF Vun-
Voo = HN, t, = tr= 20ns:
Von _ 415V, t, = tt = Mns.
VIN + ViL
2. TIMING MEASUREMENT REFERENCE LEVEL Is 2—
PARAMETER DEFINITIONS
RESOLUTION (n)
The resolution of a DAG is the number of states (2n) that the
full-scale range (FSR) is divided (or resolved) into; where n is
equal to the number of bits.
RELATIVE ACCURACY (INL)
Relative accuracy, or integral nonlinearity, is the maximum
deviation of the analog output (from the ideal) from astraight
REV. B
line drawn between the end points. " is expressed in terms of
least significant bit (LSB), or as a percent of full scale.
DIFFERENTIAL NONLINEARITY (DNL)
Differential nonlinearity is the worst case deviation of any
adjacent analog output from the ideal 1 LSB step size. The
deviation of the actual "step size" from the ideal stepsize of 1
L38 is called the differential nonlinearity error or DNL. DACs
with DNL greater than :1 LSB may be nonmonotonic. tl/2
LSB INL guarantees monotonicity and i1 LSB maximum
GAIN ERROR (Gpsg)
Gain error is the difference between the actual and the ideal
analog output range, expressed as a percent of tull-scale or
in terms of LSB value. It is the deviation in slope of the DAC
transfer characteristic from ideal.
Refer to PMI 1990/91 Data Book, Section 11 , for additional digi-
tal-to-analog converter definitions.
GENERAL CIRCUIT DESCRIPTION
CONVERTER SECTION
The DAC-8221 incorporates two multiplying 12-bit current
output CMOS digital-to-analog converters on one monoli-
thicchip. It containstwo highly-stablethin-film R-2R resistor-
ladder networks, two 12-bit DAC registers, and one 12-bit
input buffer. It also contains the DAC control logic circuitry
and 24 single-pole, doubIe-throw NMOS transistor current
switches.
