DAC8143FP-DAC8143FS Fast Delivery |IC PHOENIX CO.,LIMITED

DAC8143FP ,12-Bit Serial Daisy-Chain CMOS D/A Converterfeatures serial data input and buffered serial dataoutput. It was designed for multiple serial DAC ..
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DAC8143FP-DAC8143FS
12-Bit Serial Daisy-Chain CMOS D/A Converter
REV.C12-Bit Serial Daisy-Chain
CMOS D/A Converter
FUNCTIONAL BLOCK DIAGRAM
VDD
RFB
IOUT1
IOUT2
AGND
SRO
DGND
SRI
STB2
STB3
STB4
STB1
LD2
LD1
VREF
CLR
Figure 1.Multiple DAC8143s with Three-Wire Interface
FEATURES
Fast, Flexible, Microprocessor Interfacing in Serially
Controlled Systems
Buffered Digital Output Pin for Daisy-Chaining
Multiple DACs
Minimizes Address-Decoding in Multiple DAC
Systems—Three-Wire Interface for Any Number of DACs
One Data Line
One CLK Line
One Load Line
Improved Resistance to ESD
–408C to +858C for the Extended Industrial Temperature
Range
APPLICATIONS
Multiple-Channel Data Acquisition Systems
Process Control and Industrial Automation
Test Equipment
Remote Microprocessor-Controlled Systems
GENERAL INFORMATION
The DAC8143 is a 12-bit serial-input daisy-chain CMOS D/A
converter that features serial data input and buffered serial data
output. It was designed for multiple serial DAC systems, where
serially daisy-chaining one DAC after another is greatly simplified.
The DAC8143 also minimizes address decoding lines enabling
simpler logic interfacing. It allows three-wire interface for any
number of DACs: one data line, one CLK line and one load line.
Serial data in the input register (MSB first) is sequentially
clocked out to the SRO pin as the new data word (MSB first) is
simultaneously clocked in from the SRI pin. The strobe inputs
are used to clock in/out data on the rising or falling (user
selected) strobe edges (STB1, STB2, STB3, STB4).
When the shift register’s data has been updated, the new data
word is transferred to the DAC register with use of LD1 and
LD2 inputs.
Separate LOAD control inputs allow simultaneous output up-
dating of multiple DACs. An asynchronous CLEAR input
resets the DAC register without altering data in the input
register.
Improved linearity and gain error performance permits reduced
circuit parts count through the elimination of trimming compo-
nents. Fast interface timing reduces timing design considerations
while minimizing microprocessor wait states.
The DAC8143 is available in plastic packages that are compat-
ible with autoinsertion equipment.
Plastic packaged devices come in the extended industrial tem-
perature range of –40°C to +85°C.
ELECTRICAL CHARACTERISTICS
(@ VDD = +5 V; VREF = +10 V; VOUT1 = VOUT2 = VAGND = VDGND = 0 V; TA = Full Temperature
Range specified under Absolute Maximum Ratings, unless otherwise noted.)
DAC8143–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
STB1 Pulsewidth (STB1 = 80 ns)
STB2 Pulsewidth (STB2 = 100 ns)
STB3 Pulsewidth (STB3 = 80 ns)
STB4 Pulsewidth (STB4 = 80 ns)
Load Pulsewidth
POWER SUPPLY
NOTESAll grades are monotonic to 12 bits over temperature.Using internal feedback resistor.Guaranteed by design and not tested.Applies to IOUT1; all digital inputs = VIL, VREF = +10 V; specification also applies for IOUT2 when all digital inputs = VIH.VREF = +10 V, all digital inputs = 0 V.Calculated from worst case RREF: IZSE (in LSBs) = (RREF · ILKG · 4096) /VREF.Absolute temperature coefficient is less than +300 ppm/°C.IOUT, Load = 100 W. CEXT = 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to 1/2 LSB: tS = propagation delay (tPD) +9 t, where t equals measured
time constant of the final RC decay.All digital inputs = 0 V.VREF = 0 V, all digital inputs = 0 V to VDD or VDD to 0 V.Calculations from en = √4K TRB where:
K = Boltzmann constant, J/KR = resistance W
T = resistor temperature, K B = bandwidth, HzDigital inputs are CMOS gates; IIN typically 1 nA at +25°C.Measured from active strobe edge (STB) to new data output at SRO; CL = 50 pF.Minimum low time pulsewidth for STB1, STB2, and STB4, and minimum high time pulsewidth for STB3.
Specifications subject to change without notice.
(@ VDD = +5 V; VREF = +10 V; VOUT1 = V0UT2 = VAGND = VDGND = 0 V; TA = Full
Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.)
DAC8143
DAC8143
PIN CONNECTIONS
16-Lead Epoxy Plastic DIP
16-Lead SOIC
IOUT1RFB
IOUT2VREF
AGNDVDD
STB1CLR
LD1DGND
SROSTB4
SRISTB3
STB2LD2
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted.)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+17 V
VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–25 V
VRFB to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–25 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . .VDD + 0.3 V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . .VDD + 0.3 V
Digital Input Voltage Range . . . . . . . . . . . . . . .–0.3 V to VDD
Output Voltage (Pin 1, Pin 2) . . . . . . . . . . . . . .–0.3 V to VDD
Operating Temperature Range
FP/FS Versions . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°CJA is specified for worst case mounting conditions, i.e., qJA is specified for
device in socket for P-DIP package; qJA is specified for device soldered to
printed circuit board for SOIC package.
CAUTIONDo not apply voltage higher than VDD or less than DGND po-
tential on any terminal except VREF (Pin 15) and RFB (Pin 16).The digital control inputs are Zener-protected; however,
permanent damage may occur on unprotected units from
high energy electrostatic fields. Keep units in conductive
foam at all times until ready to use.Use proper antistatic handling procedures.Absolute Maximum Ratings apply to packaged devices.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device.
ORDERING GUIDE
Die Size: 99 · 107 mil, 10,543 sq. mils.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8143 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
FREQUENCY – Hz
THD – dB
THD – %
1001k10k100k
Figure 3.Multiplying Mode Total Harmonic
Distortion vs. Frequency
ALL BITS ON
FREQUENCY – Hz
B10
ATTENUATION – dB
(MSB) B11
(LSB) B0
DATA BITS "ON"
(ALL OTHER
DATA BITS "OFF")10k100k1M10M
108
Figure 2.Multiplying Mode Frequency
Response vs. Digital Code
VIN – Volts
IDD
– mA2345
Figure 4.Supply Current vs. Logic
Input Voltage
VDD – Volts
THRESHOLD VOLTAGE – Volts
–0.857911131715
Figure 7.Logic Threshold Voltage
vs. Supply Voltage
DIGITAL INPUT CODE – Decimal
LINEARITY ERROR – LSB
1024204830724095153625603584512
Figure 5.Linearity Error vs. Digital
Code
VREF – Volts
DNL – LSB810
–0.5
Figure 8.DNL Error vs. Reference
Voltage
VREF – Volts
INL – LSB810
–0.5
Figure 6.Linearity Error vs. Refer-
ence Voltage
SRO – VOLTAGE OUT – Volts
SINK
SOURCE
OUTPUT CURRENT – mA
Figure 9.Digital Output Voltage vs.
Output Current
DAC8143
DEFINITION OF SPECIFICATIONS
RESOLUTION
The resolution of a DAC is the number of states (2n) into which
the full-scale range (FSR) is divided (or resolved), where “n” is
equal to the number of bits.
SETTLING TIME
Time required for the analog output of the DAC to settle to
within 1/2 LSB of its final value for a given digital input stimu-
lus; i.e., zero to full-scale.
GAIN
Ratio of the DAC’s external operational amplifier output voltage
to the VREF input voltage when all digital inputs are HIGH.
FEEDTHROUGH ERROR
Error caused by capacitive coupling from VREF to output.
Feedthrough error limits are specified with all switches off.
OUTPUT CAPACITANCE
Capacitance from IOUT1 to ground.
OUTPUT LEAKAGE CURRENT
Current appearing at IOUT1 when all digital inputs are LOW, or
at IOUT2 terminal when all inputs are HIGH.
GENERAL CIRCUIT INFORMATION
The DAC8143 is a 12-bit serial-input, buffered serial-output,
multiplying CMOS D/A converter. It has an R-2R resistor lad-
der network, a 12-bit input shift register, 12-bit DAC register,
control logic circuitry, and a buffered digital output stage.
The control logic forms an interface in which serial data is
loaded, under microprocessor control, into the input shift regis-
ter and then transferred, in parallel, to the DAC register. In
addition, buffered serial output data is present at the SRO pin
when input data is loaded into the input register. This buffered
data follows the digital input data (SRI) by 12 clock cycles and
is available for daisy-chaining additional DACs.
An asynchronous CLEAR function allows resetting the DAC
register to a zero code (0000 0000 0000) without altering data
stored in the registers.
A simplified circuit of the DAC8143 is shown in Figure 10. An
inversed R-2R ladder network consisting of silicon-chrome,
thin-film resistors, and twelve pairs of NMOS current-steering
switches. These switches steer binarily weighted currents into
either IOUT1 or IOUT2. Switching current to IOUT1 or IOUT2 yields
a constant current in each ladder leg, regardless of digital input
code. This constant current results in a constant input resis-
tance at VREF equal to R (typically 11 kW). The VREF input may
be driven by any reference voltage or current, ac or dc, that is
within the limits stated in the Absolute Maximum Ratings chart.
The twelve output current-steering switches are in series with
the R-2R resistor ladder, and therefore, can introduce bit errors.
It was essential to design these switches such that the switch
“ON” resistance be binarily scaled so that the voltage drop
across each switch remains constant. If, for example, Switch 1
of Figure 10 was designed with an “ON” resistance of 10 W,
Switch 2 for 20 W, etc., a constant 5 mV drop would then be
maintained across each switch.
To further ensure accuracy across the full temperature range,
permanently “ON” MOS switches were included in series with
the feedback resistor and the R-2R ladder’s terminating resistor.
The Simplified DAC Circuit, Figure 10, shows the location of
these switches. These series switches are equivalently scaled to
two times Switch 1 (MSB) and top Switch 12 (LSB) to main-
tain constant relative voltage drops with varying temperature.
During any testing of the resistor ladder or RFEEDBACK (such as
incoming inspection), VDD must be present to turn “ON” these
series switches.
Figure 10.Simplified DAC Circuit

Partno	Mfg	Dc	Qty	Available	Descript
DAC8143FP	AD	N/a	2667	avai	12-Bit Serial Daisy-Chain CMOS D/A Converter
DAC8143FS	AD	N/a	176	avai	12-Bit Serial Daisy-Chain CMOS D/A Converter
DAC8143FS	PMI	N/a	1393	avai	12-Bit Serial Daisy-Chain CMOS D/A Converter
DAC8143FS	ADI	N/a	32	avai	12-Bit Serial Daisy-Chain CMOS D/A Converter