DAC8043 ,12-Bit Serial Input Multiplying CMOS D/A ConverterCHARACTERISTICSspecified under Absolute Maximum Ratings unless otherwise noted).DAC8043Parameter Sy ..
DAC8043AES ,12-Bit Serial Input Multiplying D/A ConverterCHARACTERISTICSDD REF AParameter Symbol Condition E Grade F Grade UnitsSTATIC PERFORMANCEResolution ..
DAC8043AES ,12-Bit Serial Input Multiplying D/A ConverterSpecifications subject to change without notice.–2– REV. 0DAC8043APIN FUNCTION DESCRIPTIONSABSOLUTE ..
DAC8043AFSZ ,12-Bit Current-Out DAC in TSSOP-8 PackageSpecifications subject to change without notice.–2– REV. ADAC8043APIN FUNCTION DESCRIPTIONSABSOLUTE ..
DAC8043EZ ,12-Bit Serial Input Multiplying CMOS D/A Converterapplications requiring an asynchronous CLEAR function or moreGND 6 11 LDversatile microprocessor in ..
DAC8043FP ,12-Bit Serial Input Multiplying CMOS D/A ConverterCHARACTERISTICS (NOTES 5, 14)Data Setup Time t T = Full Temperature Range 40 nsDS AData Hold Time t ..
DM54121J ,One-Shot with Clear and Complementary OutputsFeatures few nano-seconds to 28 seconds by choosing appropriateY R andC combinations.Therearethreet ..
DM54145J ,7 V, BCD to decimal decoder/driverFeatures
l Full decoding of input logic
I 80 mA sink-current capability
I All outputs are ..
DM54150 ,Data Selectors/MultiplexersfeaturescomplementaryWandYoutputs,where-150 11 nsas the 150 has an inverted (W) output only.151A 9 ..
DM54150 ,Data Selectors/MultiplexersFeaturesY150 selects one-of-sixteen data linesThese data selectors/multiplexers contain full on-chi ..
DM54151AJ ,Data selector/multiplexer.featurescomplementaryWandYoutputs,where-150 11 nsas the 150 has an inverted (W) output only.151A 9 ..
DM54157J ,Quad 2-Line to 1-Line Data Selectors/Multiplexers54157/DM54157/DM74157Quad2-Lineto1-LineDataSelectors/MultiplexersJune198954157/DM54157/DM74157Quad2 ..
DAC8043
12-Bit Serial Input Multiplying CMOS D/A Converter
REV.C
12-Bit Serial Input
Multiplying CMOS D/A Converter
FUNCTIONAL BLOCK DIAGRAM
PIN CONNECTIONS
8-Pin Epoxy DIP
(P-Suffix)
8-Pin Cerdip
(Z-Suffix)
16-Lead Wide-Body SOL
(S-Suffix)8TOP VIEW
(Not to Scale)
DAC8043
NC = NO CONNECT
CLK
VDD
N.C.
N.C.
N.C.
SRI
N.C.
N.C.
N.C.
VREF
RFB
IOUT
GND
GND
N.C.
GENERAL DESCRIPTIONThe DAC8043 is a high accuracy 12-bit CMOS multiplying
DAC in a space-saving 8-pin mini-DIP package. Featuring serial
data input, double buffering, and excellent analog performance,
the DAC8043 is ideal for applications where PC board space is
at a premium. Also, improved linearity and gain error performance
permit reduced parts count through the elimination of trimming
components. Separate input clock and load DAC control lines
allow full user control of data loading and analog output.
The circuit consists of a 12-bit serial-in, parallel-out shift regis-
ter, a 12-bit DAC register, a 12-bit CMOS DAC, and control
logic. Serial data is clocked into the input register on the rising
edge of the CLOCK pulse. When the new data word has been
clocked in, it is loaded into the DAC register with the LD input
pin. Data in the DAC register is converted to an output current
by the D/A converter.
The DAC8043’s fast interface timing may reduce timing design
considerations while minimizing microprocessor wait states. For
applications requiring an asynchronous CLEAR function or more
versatile microprocessor interface logic, refer to the PM-7543.
Operating from a single +5 V power supply, the DAC8043 is
the ideal low power, small size, high performance solution to
many application problems. It is available in plastic and cerdip
packages that are compatible with auto-insertion equipment.
FEATURES
12-Bit Accuracy in an 8-Pin Mini-DIP
Fast Serial Data Input
Double Data Buffers
Low 61/2 LSB Max INL and DNL
Max Gain Error: 61 LSB
Low 5 ppm/8C Max Tempco
ESD Resistant
Low Cost
Available in Die Form
APPLICATIONS
Autocalibration Systems
Process Control and Industrial Automation
Programmable Amplifiers and Attenuators
Digitally-Controlled Filters
DAC8043–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VDD = +5V; VREF = +10 V; IOUT = GND = 0 V; TA = Full Temperature Range
specified under Absolute Maximum Ratings unless otherwise noted).
NOTES
11±1/2 LSB = ±0.012% of full scale.
12All grades are monotonic to 12-bits over temperature.
13Using internal feedback resistor.
14Applies to IOUT; All digital inputs = 0 V.
15Guaranteed by design and not tested.
16IOUT Load = 100 Ω, CEXT = 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to 1/2 LSB; tS = propagation delay (tPD) + 9τ where τ = measured time
constant of the final RC decay.
17VREF = +10 V, all digital inputs = 0 V.
18Absolute temperature coefficient is less than +300 ppm/°C.
19Digital inputs are CMOS gates; IIN is typically 1 nA at +25°C.
10VREF = 0 V, all digital inputs = 0 V to VDD or VDD to 0 V.
11All digit inputs = 0 V.
12Calculated from worst case RREF: IZSE (in LSBs) = (RREF × ILKG × 4096)/VREF.
13Calculations from en = √4K TRB where: K = Boltzmann constant, J/°K, R = resistance, Ω, T = resistor temperature, °K, B = bandwidth, Hz.
14Tested at VIN = 0 V or VDD.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+17 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25 V
VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25 V
Digital Input Voltage Range . . . . . . . . . . . . . . .–0.3 V to VDD
Output Voltage (Pin 3) . . . . . . . . . . . . . . . . . . .–0.3 V to VDD
Operating Temperature Range
AZ Versions . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
EZ/FZ/FP Versions . . . . . . . . . . . . . . . . . . .–40°C to +85°C
GP Version . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . .+300°C
*uJA is specified for worst case mounting conditions, i. e., uJA is specified for device
in socket for cerdip and P-DIP packages.
CAUTIONDo not apply voltages higher than VDD or less than GND po-
tential on any terminal except VREF (Pin 1) and RFB (Pin 2).The digital control inputs are Zener-protected; however, per-
manent damage may occur on unprotected units from high
energy electrostatic fields. Keep units in conductive foam at
all times until ready to use.Use proper antistatic handling procedures.Absolute Maximum Ratings apply to both packaged devices
and DICE. Stresses above those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the device.
ORDERING GUIDE1NOTESAll commercial and industrial temperature range parts are available with burn-in.For devices processed in total compliance to MIL-STD-883, add/883 after part
number. Consult factory for 883 data sheet.
DAC8043
DAC8043
WAFER TEST LIMITS@ VDD = +5 V, VREF = +10 V; IOUT = GND = 0 V, TA = +258C.NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
DICE CHARACTERISTICSDIE SIZE 0.116 × 0.109 inch, 12,644 sq. mils (2.95 × 2.77 mm, 8.17 sq. mm)
VREFRFBIOUTGNDLDSRI
7. CLKVDD
Substate (die backside) is internally connected to VDD.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8043 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TYPICAL PERFORMANCE CHARACTERISTICSSupply Current vs. Logic Input VoltageLinearity Error vs. Digital CodeLinearity Error vs. Reference Voltage
Gain vs. Frequency (Output Amplifier: OP42)
Logic Threshold Voltage vs. Supply Voltage
Total Harmonic Distortion vs. Frequency
(Multiplying Mode)
DNL Error vs. Reference Voltage
DAC8043Figure 1.Digital Input Protection
The digital circuitry forms an interface in which serial data can
be loaded under microprocessor control into a 12-bit shift regis-
ter and then transferred, in parallel, to the 12-bit DAC register.
A simplified circuit of the DAC8043 is shown in Figure 2. An
inverted R-2R ladder network consisting of silicon-chrome,
highly-stable (+50 ppm/°C) thin-film resistors, and twelve pairs
of NMOS current-steering switches.
These switches steer binarily weighted currents into either IOUT
or GND; this yields a constant current in each ladder leg, regard-
less of digital input code. This constant current results in a con-
stant input resistance at VREF equal to R. The VREF input may
be driven by any reference voltage or current, ac or dc that is
within the limits stated in the Absolute Maximum Ratings.
The twelve output current-steering NMOS FET switches are in
series with each R-2R resistor, they can introduce bit errors if all
are of the same RON resistance value. They were designed such
that the switch “ON” resistance be binarily scaled so that the
voltage drop across each switch remains constant. If, for ex-
ample, switch 1 of Figure 2 was designed with an “ON” resis-
tance of 10 Ω, switch 2 for 20 Ω, etc., a constant 5 mV drop will
then be maintained across each switch.
Write Cycle Timing Diagram
PARAMETER DEFINITIONS
INTEGRAL NONLINEARITY (INL)This is the single most important DAC specification. ADI mea-
sures INL as the maximum deviation of the analog output (from
the ideal) from a straight line drawn between the end points. It
is expressed as a percent of full-scale range or in terms of LSBs.
Refer to PMI 1988 Data Book section 11 for additional digital-
to-analog converter definitions.
INTERFACE LOGIC INFORMATIONThe DAC8043 has been designed for ease of operation. The
timing diagram illustrates the input register loading sequence.
Note that the most significant bit (MSB) is loaded first.
Once the input register is full, the data is transferred to the
DAC register by taking LD momentarily low.
DIGITAL SECTIONThe DAC8043’s digital inputs, SRI, LD, and CLK, are TTL
compatible. The input voltage levels affect the amount of cur-
rent drawn from the supply; peak supply current occurs as the
digital input (VIN) passes through the transition region. See the
Supply Current vs. Logic Input Voltage graph located under the
typical performance characteristics curves. Maintaining the digi-
tal input voltage levels as close as possible to the supplies, VDD
and GND, minimizes supply current consumption.
The DAC8043’s digital inputs have been designed with ESD re-
sistance incorporated through careful layout and the inclusion of
input protection circuitry. Figure 1 shows the input protection
diodes and series resistor; this input structure is duplicated on
each digital input. High voltage static charges applied to the in-
puts are shunted to the supply and ground rails through forward
biased diodes. These protection diodes were designed to clamp
the inputs to well below dangerous levels during static discharge
conditions.
GENERAL CIRCUIT INFORMATIONThe DAC8043 is a 12-bit multiplying D/A converter with a very
low temperature coefficient. It contains an R-2R resistor ladder
network, data input and control logic, and two data registers.
