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DAC7718SPAG-DAC7718SRGZT
Octal, Low power,12-bit, +/-16.5V Output Serial Input Digital-to-Analog Converter
DAC7718
DAC7718IOVDD DGND
www.ti.com SBAS361A –MAY 2009–REVISED DECEMBER 2009
Octal, 12-Bit, Low-Power, High-Voltage Output, Serial Input
DIGITAL-TO-ANALOG CONVERTER
Checkfor Samples: DAC7718
2345• Bipolar Output: ±2Vto ±16.5V The DAC7718 is a low-power, octal, 12-bit
digital-to-analog converter (DAC). With a 5V
• Unipolar Output: 0Vto +33Vreference, the output can either bea bipolar ±15V
• 12-Bit Resolution voltage when operating from dual ±15.5V (or higher)
• Low Power: 14.4mW/Ch (Bipolar Supply) power supplies, ora unipolar 0V to +30V voltage
Relative Accuracy:1 LSB Max when operating froma +30.5V (or higher) power
supply. Witha 5.5V reference, the output can either
• Low Zero/Full-Scale Error:±1 LSB Max bea bipolar ±16.5V voltage when operating from dual
• Flexible System Calibration ±17V (or higher) power supplies,ora unipolar 0Vto
Low Glitch: 4nV-s +33V voltage when operating froma +33.5V (or
higher) power supply. This DAC provides low-power
• Settling Time: 15ms operation, good linearity, and low glitch over the
• Channel Monitor Output specified temperature rangeof –40°Cto +105°C. This
• Programmable Gain: x4/x6 deviceis trimmedin manufacturing and has very low
zero-code and gain error.In addition, system level
• Programmable Offset calibration can be performed over the entire signal
• SPI™: Upto 50MHz, 1.8V/3V/5V Logic chain. The output range can be offset by using the
• Schmitt Trigger Inputs DAC offset register.
Daisy-Chain with Sleep Mode Enhancement The DAC7718 featuresa standard, high-speed serial
• Packages: QFN-48 (7x7mm), TQFP-64 peripheral interface (SPI) that operates at up to
(10x10mm) 50MHz andis 1.8V, 3V, and 5V logic compatible,to
communicate witha DSP or microprocessor. The
input data of the device are double-buffered. An
APPLICATIONSasynchronous load input (LDAC) transfers data from
• Automatic Test Equipment the DAC data register to the DAC latch. The
• PLC and Industrial Process Control asynchronous CLR input sets the outputofall eight
• Communications DACsto AGND. The VMON pinisa monitor output
that connectsto the individual analog outputs, the
offset DAC, the reference buffer outputs, and twoa multiplexer (mux). and function-compatible DAC8218 (14-bit).
