DAC5674IPHP ,14-Bit, 400 CommsDAC, 2x/4x Interpolation FiltersFEATURES20 mA 200-MSPS Maximum Input Data Rate On-Chip 1.2-V Reference 400-MSPS Maximum Update R ..
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DAC5675AIPHP ,14-Bit, 400-MSPS Digital-to-Analog Converter 48-HTQFP -40 to 85features a low differential voltage swing• Differential Scalable Current Sink Outputs: 2mA towith a ..
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DAC5674IPHP-DAC5674IPHPG4
14-Bit, 400 CommsDAC, 2x/4x Interpolation Filters
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FEATURES 200-MSPS Maximum Input Data Rate 400-MSPS Maximum Update Rate DAC 76-dBc SFDR Over Full First Nyquist Zone
With Single Tone Input Signal (Fout = 21 MHz) 74-dBc ACPR W-CDMA at 15.36 MHz IF 69-dBc ACPR W-CDMA at 30.72 MHz IF Selectable 2� or 4� Interpolation Filter
− Linear Phase
− 0.05-dB Pass-Band Ripple
− 80-dB Stop-Band Attenuation
− Stop-Band Transition 0.4−0.6 F data − Interpolation Filters Configurable in Either
Low-Pass or High-Pass Mode, Allows For
Selection High-Order Images On-Chip 2�/4� PLL Clock Multiplier, PLL
Bypass Mode Differential Scalable Current Outputs: 2 mA to
20 mA On-Chip 1.2-V Reference 1.8-V Digital and 3.3-V Analog Supply
Operation 1.8/3.3-V CMOS Compatible Interface Power Dissipation: 435 mW at 400 MSPS Package: 48-Pin TQFP
APPLICATIONS Cellular Base Transceiver Station Transmit
Channel
− CDMA: W-CDMA, CDMA2000, IS-95
− TDMA: GSM, IS-136, EDGE/UWC-136 Test and Measurement: Arbitrary Waveform
Generation Direct Digital Synthesis (DDS) Cable Modem Termination System
DESCRIPTIONThe DAC5674 is a 14-bit resolution, high-speed, digital-to-analog converter (DAC) with integrated interpolation filter, onboard clock multiplier, and on-chip voltage reference. The device has been designed
for high-speed digital data transmission in wired and wireless communication systems, high-frequency
direct-digital synthesis (DDS) and waveform reconstruction in test and measurement applications.
The 4× interpolation filter is implemented as a cascade of two 2× interpolation filters, each of which can be
configured for either low-pass or high-pass response. This enables the user to select one of the higher order
images present at multiples of the input data rate clock while maintaining a low date input rate. The resulting
high IF output frequency allows the user to omit the conventional first mixer in heterodyne transmitter
architectures and directly up-convert to RF using only one mixer, thereby reducing system complexity and
costs.
In 4× interpolation low-pass response mode, the DACs excellent spurious free dynamic range (SFDR) at
intermediate frequencies located in the first Nyquist zone (up to 40 MHz) allows for multicarrier transmission
in cellular base transceiver stations (BTS). The low-pass interpolation mode thereby relaxes image filter
requirements by filtering out the images in the adjacent Nyquist zones.
The DAC5674 PLL clock multiplier controls all internal clocks for the digital filters and DAC core. The differential
clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is
supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock
divider of the PLL ensures that the digital filters operate at the correct clock frequencies.
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