DAC1265LCJ ,+/-18 V, hi-speed 12-bit D/A converter with referenceElectrical Characteristics VsupPLy= i 15V , 5% unless otherwise noted. Boldface Ilmlla apply over ( ..
DAC1266LCJ ,0 V to -18 V, hi-speed 12-bit D/A converterFeatures
I Bipolar current output DAC
I Fully differential, non-saturating precision current sw ..
DAC128S085CIMT/NOPB ,12-Bit Micro Power OCTAL Digital-to-Analog Converter with Rail-to-Rail Outputs 16-TSSOP -40 to 125Features 3 DescriptionThe DAC128S085 is a full-featured, general-purpose1• Ensured MonotonicityOCTA ..
DAC1405D750HW , Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
DAC1408A8Q ,V(cc): +5.5V; 8-bit multiplying D/A converterCHARACTERISTICS at Vcc = +51/dc, VEE = -15Vdc, VHEF/Fi14 = 2mA, 0°C s T, s +75°C for DAC-1408A, unl ..
DAC1408A8Q ,V(cc): +5.5V; 8-bit multiplying D/A converterapplications Mxibility your
attention is directed to the DAC-08 8-bit high-speed multiplying
D/A ..
DL5238 , 500 mW Zener Diode 2.4 to 200 Volts
DL5239 , 500 mW Zener Diode 2.4 to 200 Volts
DL5240 , 500 mW Zener Diode 2.4 to 200 Volts
DL5240 , 500 mW Zener Diode 2.4 to 200 Volts
DL5241 , 500 mW Zener Diode 2.4 to 200 Volts
DL5242 , 500 mW Zener Diode 2.4 to 200 Volts
DAC1265LCJ
+/-18 V, hi-speed 12-bit D/A converter with reference
National
[ Semiconductor
DAC1265A/DAC1265 Hi-Speed 12-Bit D/A Converter
with Reference
General Description
The DAC1265A and DAC1265 are fast 12-bit digital to ana-
log conveders with internal voltage reference. These DACs
use 12 precision high speed bipolar current steering
switches, control amplifier, thin film resistor network, and
buried zener voltage reference to obtain a high accuracy.
very fast analog output current. The DAC1265A and
DAC1265 have 10%-90% full-scale transition time under
35 ns and settle to less than y, LSB in 200 us. The buried
zener reference has Iong-term stability and temperature drift
characteristics comparable to the best discrete or separate
IC references.
These digital to analog converters are recommended for
applications in CRT displays, precision instruments and data
acquisition systems requiring throughput rates as high as 5
MHz for full range transitions.
Features
I: Bipolar current output DAC and voltage reference
a Fully differential, non-saturating precision current switch
- ROUT and Com do not change with digital input
I: Internal buried zener reference - 10Vi1% max
I: Precision thin film resistors for use with external op
amp fdr voltage out or as input resistors for a succes-
sive approximation A/D converter
l: Superior replacement for 12-bit D/A converters of this
Key Specifications
n Resolution and Monotonicity 12 Bits
n Linearity 12 Bits
(Guaranteed over temperature)
a Output Current Settling Time 400 ns max to 0.01%
" Gain Tempco i 15 ppmf''C max
a Power Supply Sensitivity i 10 ppm of FS/% VSUPPLY
Block and Connection Diagrams
Ws BID -itg It "
, It , t
= -.-et', m mm:
IREF i i u tity mum:
nlmtuc: r', Ae 'Ae
ll?!” " "
I II - I
"Ir/gt-i-. Italy m. t'l'l1tfJg,'g%
I mm =
'l'llk,t o-----,
6666666 6
11132121101! IIIT Ii" n [
(Mm MI} TL/H/5242-1
Dual-ln-Line Package
uc- 1 24 Husi0trr1
nc- 2 23 -arr2
"r s 22 -8it3
10.0Yesr WT‘ ' 21 '3'” Order Number DAC1265AJ.
“MGWD' 5 20 -etts DAtM265ACd, DAC1265LJ or
REFINPUT- o 19 -8tt6 DAC1265LCJ
-vs- 7 18 -ern Stttt NS Package Number J24A
ummorrsn- a 17 -otr8
lom(-2mAFS)- ' 15 -titr'
1ovmecc- IO 15 -8tTt0
20YUNtE-1t 14-arm
Powznouo- 12 13 -(LSB)BIT12
TUH/6242-2
Top View
993 LOVG/VSQZLOVG
DAC1265A/DAC1265
Absolute Maximum Ratings
" '8llitaryfAerospatte specified devices are required,
please contact the National Semiconductor Sales
Offlce/Dlstrlbutors for availability and ttpetMttatloms,
Supply Voltage (V + and V-) 1 18V
Current Output (Pin 9) Voltage - 3V, 12V
Logic Input Voltage - IV, 7V
Reference Input Voltage (Pin 6) i 12V
Analog GND to Power GND 11V
Bipolar Offset l 12V
10V Range i 12V
20V Range v- to + 24V
Power Dissipation (Note 1) 1000 mW
Short-Circuit Duration (Pins 4 to 12) Continuous
Operating Temperature Range
DAC1265AJ, DAC1265LJ
DAC1 265ACJ, DAC1 265LCJ
Storage Temperature Range
TMINSTAS TMAX
--55% to + 125°C
tPG to + 70'C
-65% to + 15ty'C
Maximum Junction Temperature 150°C
Lead Temperature (Soldering, 10 seconds) 300°C
ESD Susceptibility (Note 13) TBD
Electrical Characteristics VsuppLy= k151/ i 5% unless otherwise noted. Boldface llmlts apply over tem-
perature, Tum s; TA STqu. For all other limits TA == 25''C.
DAC1265A DAc1265
Parameter Conditions See Tested Design Tested Design Units
Note Typ leIt Llmlt Typ Llmlt Limit
(Note 11) (Note 2) (Note 3) (Note 11) (Note 2) (Nate 3)
CONVERTER CHARACTERISTICS
Resolution 12 12 Bits
Linearity Error Zero and Full-Scale Adjusted 4 LSB
Max i Va i V4 l y, 1 y,
AJ and Ll Suffix Parts i y, i %
ACJ and LCJ Suffix Parts l y, 1- %
Differential Zero and FuII-Scale Adjusted i V. k % i 'h i bt
Non-Linearity
Monotonicity AJ and LJ Suffix Parts 12 12 Bits
ACJ and LC) Suffix Parts 12 12 12 12
Full-Scale R2--50n in Figural 5 10.1 $0.20 10.1 $0.20 % Full-
(Gain) Error Scale
9.t.titt Error Max Unipolar (Figure 1 Pin 8 Open) 6 i 0.01 $0.05 * 0.01 k 0.05
f)ll ?:?.81: F, Bipolar (R1 and R2 = son in 7 i 0.05 d: 0.1 i 0.05 i 0.15
g Figurea
Zero Error Max Bipolar (R1 and R2 = 500 in 8 i 0.05 , 0.1 k 0.05 , 0.15
MSB ON Figure a
Gain R2--50n i500. in Figure 1 10.2 $0.2
Adjustment
Range Min
BipolarOftset R1=5002t son and R2--50n $0.15 10.15
Adjustment in Figure 2
Range Min
Full-Scale (Gain) Using the AJ and LJ Suffix 9 10 " 15 30 ppm/"C
Temperature lntemai
Coefficients Max Reference ACJ and LCJ Suffix IO 20 15 tio
Unipolar Offset AO and Ll Suffix 1 2 1 2
Temperature .
Coefficients M ax ACJ and LCJ Suffix 1 2 1 2
Bipolar Zero AJ and Ll Suffix 5 10 5 10
Temperature .
Coefficients Max ACJ and LCJ Suffix 5 10 5 10
Output Exclusive of Offset and 7.5 6 to 10 7.5 6 to 10 k0.
Resistance Range Rs
Electrical Characteristics (Continued) VsuppLY = * 15VK 5% unless otherwise noted. Boldface llmlls apply
OVBI’ temperature. Tum S TA S THAX- For all other limits TA = 25''C.
DAC1265A DAC1265
See Tested Design Tested Deslgn
Parameter CortdItlona Note Typ lelt lelt Typ Urttit Limit Units
(Note 11) (Note 2) (Note 3) (Note 11) (Note 2) (Note 3)
Current Output Unipolar - 2 - 1.6 to - 2 - 1 .6 to mA
--2.4 --2.4
Bipolar $1.0 t 0.8 to 21:10 l 0.8 to
* 1.2 * 1.2
Output 25 25 pF
Capacitance
Output Noise (FS, 10 Hz to 100 kHz with Internal 40 40 erms
1 0V Range) Reference
Typ Output Using Internal Offset and Range Rs , 2.5. * 5, 1:10, o to 5, om 10 V
Voltage Ranges
Relerence Input 20.8 15 to 25 20.8 15 to 25 kn
Resistance
Output - 1.5 to - 1.5 to v
Compliance 10 10
Voltage
REFERENCE OUTPUT CHARACTERISTICS
It:',',',""' Min IREF= 1.5 mA 10.00 9.90 10.00 9.90 V
t2 ge Max 10.10 10.10
Temperature i 8 , 1 2 pprnPC
Coefficient
Reference 3.0 3.0 mA
Output Current
Output ft: = 1 kHz, 0.5 mA S IREFS 3 mA 0.05 1.0 0.05 1.0 n
Resistance Max
DIGITAL AND DC CHARACTERISTICS
Logic Input Logic High AJ and Ll Suffix 2 to 5.5 2 to 5.5 V
Voltage Bit ON ACJ and LCJ Suffix 1.9 to 5.5 2 to 5.5 1.9 to 5.5 2to 5.5
Max Logic Low AJ and Ll Suffix 0.8 0.8
Bit OFF ACJ and LCJ Suffix 1.0 0.8 1.0 0.8
Logic Input Logic High AJ and LJ Suffix 150 300 150 300 0A
Current Max ACJ and LCJ Suffix 150 280 300 _ 150 280 300
Logic Low Ad and LI Suffix 45 100 45 100
ACJ and LCJ Suffix 45 90 100 45 90 100
Power Supply 1+ v+ Supply= 15V 1 10% 3 5 3 5 mA
GurrentMax I- V-supply==-15Vh10% -12 --18 -12 -t8
Power VsuppLy= , 15V 225 345 225 345 mW
Dissipation Max
Power Supply V+ Supply=15V l 10% 10 i 3 i 10 i 3 i 10 ppm of FS/
Sensitivity Max v- Supply= - 15V 1 10% 10 + 15 i 25 i 15 k 25 % Vsuppcy
SSMOVG/VSQZlOVG
DAC1265A/DAC1265
Electrical Characteristics (Continued) VsuppLY = i15V i 5% unless otherwise noted. Boldface limits apply
over temperature. Ttgit; STA STMAX- For all other limits TA = 25°C.
DAC1265A DAc1265
Parameter Conditions See Tested Design Tested Design Units
Note Typ Limit lelt Typ lelt Llrnit
(Note 11) (Note 2) (Note 3) (Note 11) (Note 2) (Note 3)
Ac CHARACTERISTICS
Settling FSR Change 200 400 200 400 ns
Time Max
FulI-Scale 10% to 90% Rise Time 15 30 1 5 30 ns
Transition Max Plus Delay Time
90% to 10% Fall Time 30 50 30 50
Plus Delay Time
Note 1: The typical ttA of the 24-pin package is 80. C/W.
Note 2: Tested and guaranteed to National's AOQL (Average Outgoing Quality Level).
Note & Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Vour-VorrsET - (DX VLSB) VFs-VOFFSET
VLSB 4095
(st -WrFSETI ~(4095/4096novx
Note 6: Unipolar offset error for 10V range = (VOUT/ 10V) X 100 in percent of tull-scale.
V - - V
Note r.. Bipolar offset error for 10V range-- 'lo-UT-it-sv)
Note it.. Bipolar zero error tor 10V rttngtre-(Vour/10V)x 100 in percent ot fuIl-scale.
Ms - Vowssrlat (me or Tum) -(Vi=s -VoFFSET) at 25"C
10V range M “MM or TMIN -25''t0
-v at16.5V -13. - -v t13.5V -16.5
(VFS OFFSET) ( or igyx 2/01: OFFSET)3( or 10ewpmsrs/svs.
Note 4: Linearity enor - where VLSB "' and D is the digital input (0 to 4095) which produced vour.
Note 6: Percent gain error tor 10V range - 100.
x 100 in percent of fullscale.
Note 9: Gain error tBmpco- X 103 in ppm/‘C.
Note 10: Power supply sensitivity for 10V range =' 106x
The opposite supply is held at -15V or +15V respectively.
Note " Typicals are at 25N3 and represent most likely parametric norm.
Note 12: Absokite Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical smscifieatitms do not apply when
operating the device beyond its specified operating conditions.
Note 13: Human body model, 100 pF discharged through a 1.5 kn resistor.
Functional Description and
Applications
1.0 BUFFERED VOLTAGE OUTPUT CONNECTION Step 2-Galn Adjust
The standard current-to-voltage conversion connections us- Turn all bits ON and adjust 1000 gain trimmer, R2, until the
ing an operational amplifier are shown here with the pre- output is 9.9976V (full-scale adjusted to 1 LSB less than
ferred trimming techniques. lfalow offsetoperational ampli- nominal full-scale oi 10.000V). It a 10.2375V full-scale is
tier (LF401A) is used, excellent performance can be ob- desired (exactly 2.5 mV/bil),inserta120ll resistor in series
tained in many situations without trimming (an op amp with with the gain resistor at pin 10 to the op amp output.
less than 0.5 mV maximum offset voltage should be used to
keep offset errors below 'h LSB). Unipolar zero will typically Idt Blpolar Contlguratlon (Figure 2)
be within i % LSB (plus op amp offset), and if a 50fl fixed This configuration will previde e hipolar output voltage frem
resistor is substituted for the 100ft trimmer (R2, Figure 1), - 1P?Y to 4.9976V, with positive full-scale occurring with
full-scale accuracy will be within 0.1% (0.20% maximum). all bits ON (all Is).
Substituting a tion resistor for the 100ft bipolar offset trim. Step I-offset Adjust
Hr. (RI, Figure 2) Zn" give a bipolar zero error typically Turn OFF all bits. Adjust 1000 offset trimmer, RI, to give
within :2 LSB (0.05 lo).
-5.000V output.
Step 2-Gain Adjust
I'. Unlpelar Cenflquratloh (Figure 1) Turn ON all bits. Adjust 100n gain trimmer, R2, to give a
This configuration will provide a unipolar 0V to 9.9976V out. reading Of 4.9976V.
put range. Please note that it is not necessary to trim the op amp to
obtain full accuracy at room temperature. in most bipolar
Step 1-Offaet Adjust (Zero) situations, an op amp trim is unnecessary unless the un-
Turn all bits OFF and adjust zero trimmer, R1, until the out- trimmed offset drift of the op amp iS excesswe. Bipolar zero
= . . error (MSB bit ON) is not adjusted separately and is typically
i',',ugre,s2ie.01/ (1 LSB 2.44 mV). in most cases this trim < 10.05% of FS after offset and gain adjust.
Functional Description and Applications (Continued)
15v -vsv
-"---'i REF not w; urnun 07:6 =
—o zov Mus:
m ' nAcImA Ian it
1 mcms
"m " M m nuns IOpF
A I #A‘ -
' m “c u: uuT W " m
TI" laut-lxlnnlwl}!
r cons mu! I
t It m “o tt " J' ‘Power and analog ground must have a
- s E m- - - - - - - - - -l:l common currenlretum path. Seesec-
- then 4.0 for proper connections.
TLIH/5242-3
FIGURE 1. 0V to 10V Unipolar Voltage Output
W; 18:
an 00! o Ixnun orrtf
I - a a
- =© m mm:
" h '3' {L
m ' nntmu mu it n
, - nAcms T
_ "a..,
tptr anAIas Ill
' lust M. .
REF ll f -
olul "t Int our +
“A sun G
tr at man
"IT IWT . 4 x Itttr x can: 1 u:
con: mm! I = -
1 u n 'P
- - - - - - - - - -6 ower and analog ground must have 3
mncln'}:
M"------------- LSI
FIGURE 2. l 5V Blpolar Voltage Output
common current return path. See sec-
tion 4.0 for proper connections.
TL/H/5242-ti
993l3VG/VS9ZLOVO
DAC1265AIDAC1265
Functional Description and Applications (Continued)
1.3 Other Voltage Ranges (Figure 3)
The DAC1265A and DAC1265 can also be easily configured
for a unipolar 0V to 5V range or t2.5V and :t1OV bipolar
ranges by using the additional 5k application resistor provid-
ed at the 20V range R terminal, pin 11. For a 5V range (0V
to 5V or i2.5V), the two 5k resistors are used in parallel by
shorting pin 11 to pin 9 and connecting pin 10 to the op amp
output and the bipolar offset either left open for unipolar or
connected through a 1000 pot to the REF OUT tor the bipo-
lar range. For the k 10V range use the 5k resistors in series
by connecting only pin 11 to the op amp output and con-
necting the bipolar offset as shown. The i10V option is
shown in Figure 3.
2.0 INTERNALIEXTERNAL REFERENCE USE
The performance of the DAC1265A and DAC1265 is speci-
fied with the internal reference driving the DAC since all
trimming and testing (especialiy for fuli-scale error and bipo-
lar operation) is done in this configuration.
The internal reference has sufficient buffering to drive exter-
nal circuitry in addition to the reference currents required for
the DAC (typically 0.5 mA to REF IN and 1.0 mA to BIPO-
LAR OFFSET, if used). A minimum of 1.5 mA is available for
driving external circuits. The reference is typically trimmed
to i0.2%. then tested and guaranteed to k 1.0% maximum
error. The temperature coefficient is comparable to that of
the fuli-sttale TC for a particular grade.
3.0 DIGITAL INPUT
The DAC1265A and DAC1265 use a standard positive true
straight binary code for unipolar outputs (all 1s give full-
scale output), and an offset binary code tor bipolar output
ranges. In the bipolar mode, with all Os on the inputs, the
output will go to negative full-scale, with 100...00 (only the
MSB on), the output will be 0.00V; with all Is, the output will
go to positive full-scale.
The threshold of the digital input circuitry is set at 1.4V and
does not vary with supply voltage. The input lines can inter-
face with any type oftiV logic, TTL/DTL or CMOS, and have
sufficiently low input currents to interface easily with unbuf-
fered CMOS logic. The configuration of the input circuit is
shown in Figure 4. The input line can be modeled as a 30
kn resistance connected to a -0.7V rail.
Mitt " TD MI
TO LOGIC
TL/H/5242-6
FIGURE 4. Equivalent Digital Input Circuit
mom: on
i av mm
m =, m t
m p oncum ma. at u
, - umm P
mu nu mama: 1a,;
A ' 4.. - s t. -H _
v vvv tr
an a _
nae ' 'o "tl WT "O E?mo M
An sun s'
, " mm
IL". lmn-ll in“ I COOE "
m tam',
o----_-_---b
"lt------------"'
'Power and analog ground must have a
common current return path. See seo-
tion 4.0 for proper connections.
TLYH/5242-4
FIGURE 3. i 10V Voltage Output
4-1 20
Functional Description and Applications (Continued)
4.0 APPLICATION OF ANALOG AND POWER GROUNDS
The DAC1265A and DAC1265 have separate analog and
power ground pins to allow optimum connections for low
noise and high speed performance. The two ground lines
can be separated by up to 200 mV without any loss in per-
formance. There may be some loss in linearity beyond that
level. If these DACs are to be used in a system in which the
two grounds will be ultimately connected at some distance
from the device, it is recommended that parallel back-to.
back diodes be connected between the ground lines near
the device to prevent a fault condition.
The analog ground at pin 5 is the ground reference point for
the internal reference and is thus the "high quality" ground;
it should be connected directly to the analog reference point
of the system. The power ground at pin 12 can be connect-
ed to the most Convenient ground reference point; analog
power return is preferred, but digital ground is acceptable. If
power ground contains high frequency noise beyond 200
mV, this noise may feed through the converter, so that
some caution will be required in applying these grounds.
5.0 OUTPUT VOLTAGE COMPLIANCE
The DAC1265A and DACI 265 have a typical output compli-
ance range from -2V to 10V. The current-steering output
stages wilt be unaffected by changes in the output terminal
voltage over that range. However, there is an equivalent
output impedance of 8k in parallel with 25 pF at the output
terminal which produces an equivalent error current if the
voltage deviates from power ground. This is a linear effect
that does not change with input code. Operation beyond the
compliance limits may cause either output stage satura-
tion or breakdown which results in non-linear performance.
Compliance limits are not affected by the positive power
supply, but are a function of output current and negative
supply.
6.0 DIRECT UNBUFFERED VOLTAGE OUTPUT FOR CA-
BLE DRIVING
The wide compliance range allows direct current-to-voltage
conversion with just an output resistor. Figure 5 shows a
connection using the gain and bipolar output resistors to
give a _+1.60V bipolar swing. In this situation, the digital
code is complementary binary. Other combinations of inter.
nal and external output resistors (Fix) can be used to scale
to alternate voltage ranges, simply by appropriately sealing
the o mA to -2 mA unipolar output current and using the
10.0V reference voltage for bipolar offset. For example, set-
ting Rx=2.67 kn gives a A1V range with a 1 kn equivalent
output impedance.
This connection is especially useful for directly driving a
long cable at high speed. Using a son resistor for R, would
allow interface to a son cable with a $50 mV full-scale
swing.
7.0 HIGH SPEED 12~BIT AID CONVERTERS
Tho fast settling characteristics of the DAC1265A and
DAC1265 make them ideal for high speed successive ap-
proximation A/D converters. The internal reference and
trimmed internal resistors allow a 12-bit converter system to
be constructed with a minimum parts count. Shown in Fig-
ure 6 is a configuration using standard components; this
system completes a full 12-bit conversion in 10 its unipolar
or bipolar. This converter will be accurate to i y, LSB of 12
bits and have a typical gain TC of 10 ppmPC.
20V RANGE
“N RANGE I
mom o mpuunorn}
tun - nAcizasA asst?
_ nmzss
It 1N15k M,
ANA END
S2tk 4%
tggT = 4 I IREF I CODE
n" um: MT
CODE INPUT I -
, 12 "
nun sun
-lts MSB
o---------"
TL/H/5242-7
FIGURE 5. Unbuffered Bipolar Voltage Output
SSZLOVG/VSSZLOVG
DAC1265A/DAC1265
Functional Description and Applications (Continued)
In the unipolar mode, the system range is 0V to 9.9976V,
with each bit having a value of 2.44 mV. For true conversion
accuracy. an A/D converter should be trimmed so that a
given output code results from input levels from 'h LSB ber.
low to y, LSB above the exact voltage represented by that
code. Therefore, the converter zero point should be
trimmed with an input voltage of 1.22 mV; trim R1 until the
LSB just begins to appear in the output code (all other bits
"O"). For full-scale, use an input voltage of 9.9963V (10V-1
LSB-M, LSB); then trim R2 until the LSB iust begins to ap-
pear (all other bits “1").
The bipolar signal range is - 5.0V to 4.9976V. Bipolar offset
trimming is done by applying a -4.9988V input signal and
trimming R3 for the LSB transition (all other bits "O''),
Full-scale is set by applying 4.9963V and trimming R2 for
the LSB transition (all other bits "1'T In many applications,
the pretrimmed internal resistors are sufficiently accurate
that external trimmers will be unnecessary. especially in sit-
uations requiring less than full 12-bit iv, LSB accuracy.
For fastest operation, the impedance at the comparator
summing node must be minimized. However, lowering the
impedance will reduce the voltage signal to the comparator
(at an equivalent impedance at the summing node of 1 kit,
1 LSB ==0.5 mV), to the point that comparator performance
will be satmTiced. The contribution to this impedance from
the DAC will vary with the input configuration (F/gum 6, Input
Ranges Table).
To prevent dynamic errors, the input signal should have a
low dynamic source impedance, such as that of the LF4t 1A
op amp.
IIIOLAB “MINI”!
ttttrt
Rt (“NI") LAt0
m our o IINILAR or;
av nus: A Autos "mm
Ji A ttlt mi
. nncusu
- 0mm Ill n: .5 In "
'REF m tune:
I tus- " .%
V V . .
ANA 'tt-
t-' 2N {1
- iitgtoairtsr"tr"
' one out
35mm r3, '
IDDE IN'IIY
INS COT
MSB-------
vowsncuni >OOQQQOOOVO<5
mm 1 ee
SERIIL '""--,- DD
DMISM SAN
tt DM‘A ll
os'. mm
- ELDEK
" ll " It
W u ur = INPUT RANGES
lhlpolar Blpolor
TL/H/5242-8
Equlv.
Connect DAC 20m
0 to 5 1 " Input to A 1.60 kn
B to DAC OUT
Oto 10 i5 InputtoA 2.35 m
a text! 110 Input to B 3.08 kn
FIGURE 6. Fast Preclslon Analog to Digital Converter
Definition of Terms
Digital Inputs: The DAC1265A and DAC1265 accept digital
input codes in binary format and may be user connected for
any one of three binary codes: straight binary, two's comple-
ment, or offset binary.
Digital Analog Output
Ari,, Straight Offset Two's
Binary Blnary Complement‘
000 . .000 zero -- FS (Full-Scala) zero
011...111 14FS-t LSB zero--ILSB +FS--ILSB
100 . .000 y, FS zero - FS
111...111 +FS--ILSB +FS--ILSB zertr-ILSB
'Invert MSB with external invader to obtain Two's Complement cotrog
LInearlty Error: Linearity error of a BM convener is an
important measure at its accuracy. It describes the deviation
from an ideal straight line transfer curve drawn between
zero (all bits OFF) and full-scale (all bits ON).
Differential Non-Llnearlty: For a D/A converter, it is the
difference between the actual output voltage change and
the ideal (1 LSB) voltage change for a one-bit change in
code. A differential non-linearity of Al LSB or less guaran-
tees monotonlcity, i.e., the output always increases and nev-
er decreases for an increasing input. It is guaranteed by
testing the major carry transitions. i.e., 100...000 to
011...111, etc.
Settling Tlme: Settling time is the time required for the out.
put to settle to within the specified error band for any input
Ordering Information
code transition. It is usually specified for a full-scale or major
carry transition.
Gain Tempco: The change in full-scale analog output over
the specified temperature range expressed in parts per mil-
lion of full-scale per ( (ppm of FS/NO. Gain error is mea-
sured with respect to 25''C at high (T MAX) and low (T MIN)
temperatures. Gain tempco is calculated for both high
(T MAx-2tPC) and low (25'C-TMIN) ranges by dividing the
gain error by the respective change in temperature. The
specification is the larger of the two representing worst-
case drift.
Offset Tempco: The change in analog output with all bits
OFF over the specified temperature range expressed in
parts per million of full-scale per "C (ppm of FSI'C). Offset
error is measured with respect to 25'C at high (T MAX) and
low (T MIN) temperatures. Offset tempco is Calculated for
both high (T MAX-25'C) and low (25''C-Tum) ranges by
dividing the offset error by the respective change in temper-
ature. The specification given is the larger of the two, repre-
senting worst-case drift
Power Supply Sensltlvlty: Power supply sensitivity is a
measure of the change in gain and offset of the BIA con-
verter resulting from a change in -15V or + 15V supplies.
It is specified under DC conditions and expressed as parts
per million of full-scale per percent of change in power sup-
ply (ppm of FS/%).
Temperature Range trc to Ttre -55'C to + 125°C
Linearity Error 11/, Bit DAC1265ACJ DAC1265AJ
thmr Temperature , y. Bit DAC1265LCJ DAC1265LJ
SQZLOVG/VSSZLOVO
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
DAC1265LCJ - product/dac1265|cj?HQS=TI-null-nulI-dscataIog-df-pf-null-wwe
DAC1265AJ - product/dac1265aj?HQS=T|-nu|I-null-dscatalog-df—pf—nuII-wwe
DAC1265ACJ - product/dac1265acj?HQS=T|-nu|I-nuII-dscatalog-df—pf—null-wwe
DAC1265LJ - product/dac1265|j?HQS=T|—nu|l-nu|I-dscatalog-df—pf-null-wwe
