DAC1136L ,HighR esoluti1o6n- a nd1 8-Bit Digital-to-AnaClongv eftersFEATURES.itDACl138(38gV, 1 Part in 262,1441and Accuracv 18'Bit Resolution (DACI max 138K)Nonlineari ..
DAC1208LCJ ,DAC1231/DAC1232 12-Bit/ mP Compatible/Double-Buffered D to A ConvertersFeaturesYLinearity specified with zero and full-scale adjust onlyThe DAC1208 and the DAC1230 series ..
DAC1208LCJ-1 ,DAC1231/DAC1232 12-Bit/ mP Compatible/Double-Buffered D to A ConvertersFeaturesYLinearity specified with zero and full-scale adjust onlyThe DAC1208 and the DAC1230 series ..
DAC1208LCJ-1 ,DAC1231/DAC1232 12-Bit/ mP Compatible/Double-Buffered D to A ConvertersFeaturesYLinearity specified with zero and full-scale adjust onlyThe DAC1208 and the DAC1230 series ..
DAC1209LCJ ,DAC1231/DAC1232 12-Bit/ mP Compatible/Double-Buffered D to A ConvertersMICRO-DACDAC1208/DAC1209/DAC1210/DAC1230/DAC1231/DAC123212-Bit,mPCompatible,Double-BufferedDtoAConv ..
DAC1209LCJ ,DAC1231/DAC1232 12-Bit/ mP Compatible/Double-Buffered D to A ConvertersMICRO-DACDAC1208/DAC1209/DAC1210/DAC1230/DAC1231/DAC123212-Bit,mPCompatible,Double-BufferedDtoAConv ..
DL4004-13-F , 1.0A SURFACE MOUNT GLASS PASSIVATED RECTIFIER
DL4004-TP , 1 Amp Glass Passivated Rectifier 50 to 1000 Volts
DL4005-13-F , 1.0A SURFACE MOUNT GLASS PASSIVATED RECTIFIER
DL4007-13-F , 1.0A SURFACE MOUNT GLASS PASSIVATED RECTIFIER
DL401 , 100 MHz FADC
DL401 , 100 MHz FADC
DAC1136L
HighR esoluti1o6n- a nd1 8-Bit Digital-to-AnaClongv efters
ANALOGDEVICES
High Resolution 16- and 18-Bit
CERTIFICATE OF CALIBRATION
Each DACl138 has been calibrated with equipment and
methoCs that are traceable to the National Bureeu of Stand-
ards (NBS). A Certificate of Performance is sent with each
unit, which includes linearity test data.
Digital-to-Analog Convefters
:.]:;*
.it
ZERO
7I ADJUST
70 5k SENSE
69 CURRENT OUT
68 l0k sENsE
FEATURES
DACl138
18'Bit Resolution and Accuracv (38gV, 1 Part in 262,1441
Nonlinearity 1/2LSB max (DACI 138K)
Excellent Stability
Settlins to 1/2LSB (0.0002%) in 1ops
Hermetically-Sealed Sem iconductors
DAC1136
16-Bit Resolution and Accuracy n52PV,1 Part in 65,536)
Low Cost
Nonlinearity 1/2LSB max (DACI136K, L)
Settling to 1/2LSB max (0.0008%) in Qrs
DEGLITCHER IV
Eliminates DAC Glitches
Available on DACl 136/1 138 Card-Mounted Assembly
GENERAL DESCRIPTION
The DAC113 6/1138 are complete self-contained culrent or
voltage output modular digital-to-analog converters with
resolutions and accuracies of 1.6 and 18 bits'
The DAC1136/1138 combine precision current sources
with state-of-the-art steering switches to produce a very linear
output. Inputs to these converters are compatible with TTL
levels, The converters have a current output of -2mA full scale.
A voltage output can be obtained by connecting the internal
amplifier to the current output by means of jumpers. By using
additional jumpers, the user can select any one of the fol-
lowing output ranges: O to +5V,0 to +10V, l5V, or t10V.
The DAC113 6/1138 are available on Card-Mounted Assemblies.
In this configuration, selectable options include' input codes,
output amplifiers, and a high speed transient-suppressing
Deglitcher Module, Deglitcher IV.
WHERE TO USE HIGH RESOLUTION DACS
The DAC113 6lll38 deliver exceptional accuracy for a broad
range of ciisplay, test and instrumentation applications. The
DAC1136, with a resolution of 16 bits or 1 part in 65'536'
and thc DAC1138 with a resolution of 18 bits or 1 Part in
262,1++ are ideally suited for applications requiring wide
dynamic range measurement and control. Applications include
data acquisition systems' high resolution CRT displays, auto-
matic semiconductor testing, p hoto-typesetting, f re quency
synthesis and nuclear reactor control.
*DACl]38 ONLY
Figure L Block Diagram and Pin Designations
MSB
atT 2
8tT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 1O
BIT 11
BIT 12
8tr 13
gtr 14
stT 15
BIT 16
*BrT 17
'L::18
,r 5v
COMMON
53 REF IN
52 REF OUT
49 GAIN
48 GAIN
47 AMP OUT
46 tsIPOLAR
OFFSET OUTAMP IN
SPECIFICATI(INS
(typical @ + 25"C, rated power supplies unless othenyise noted; specifications for mounting cardwith
Smllif ierldeglitc her opiions same asllodule- udgss otherwise noted)
DACll36 on Mounting Card with
Amplilier/Deglitcher Options.
DACll36 Module
IKL. :- "'-^ _*..RESOLUTION, BITS
ACCURACY
Integral Nonlinearity
Differential Nonlinearity
Gain and Offset Error (Externally Adjustable)
ANALOGOUTPUT
Unipolar Mode
Bipolar Mode
Output Range (Pin Selectable)
ILSB max ilLSBmax
:: I/2LSB maxI/2LSB maxI * llzLSBmax* lz2LSB-a*
Gain, offset and glitch-nulling adjustments
provided on the mounting card.
2mA to OmAlmAto + lmA
0to +5V,0to + l0v, -!5v, t l0V
TTL/CMOS; See Figure 2
Complementary Binary (COMP BIN) | BIN, COMP BIN, 2's COMP, COMP 2's COMP
Complementary Offset Binary (COMP OBIN) I OBIN, COMP OBIN
DIGITAL INPUTS
INPUTCODES
Unipolar Mode
Bipolar Mode
STROBE INPUT
DYNAMIC CHARACTERISTICS
SettlingTineto li2LSB
Current
Full Scale Step
LSB Step
Voltage
Unipolar(l0V Step)
Bipolar (20V Step)
LSB Step
Slcw Rate
IEMPERATURE COEFFICIENTS
ppm of FStu"C)r
Inregral Nonlinearity
Differential Nonlinearity
Gain iExcluding Vp1;1.)
0ffsct
Unipolar Mode
Bipolar,\lode
iSIGN PLUS MAGBIN, COMP SIGN PLUS MAG BINOne standard series 74LS load, leading-edgeNone
90ps
250ps
8ps
lV/ps
80ps
90ps
8ps
2Vlps
25ps
30ps
8ps
20V/ps
triggered, pulse width l00ns minimum
Voltage Output, Only
Voltage Output, Only
45ps
60ps
8ps
6V/psl.5 max1.5 max
t8max
t 0.5
STABILITY, LONG TERM
,ppm ofFSRr 1,000 hrs.)2
Bipolar Mode l
Output Current (BV -- l0OkHz)
Output Voltage (BW - 0. l-lOHz)
,, 0\'iAl I I'sCode; "ZERO")
,, 5\'iMSB = 0Code;"Half Scale")
', l0\' rAl I 0's Codel "Full Scale")
0.5nA rms
4pV pk-pk
6pV pk-pk
9pV pk-pk
30pV rms
Voltage Output, Only
40pVrms I
t 50pV
:r 5pV/"C
35pV rms2mV maxl00pVl0pV/"C
via Internal Schottky Diodes
:t20pV ! tl0opv
:t0.lpV/"C i * tSrrVfCFl,x Drift
Currcnt Output (pin 69)
!oltage Protection
Source Resistance
Unipolar Mode
Bipolar Mode
Source Capacitance
RhFERENCE VOLTAGE (VRr,r.)
!oltagc I Z()r-r :200O)
\oisc.BV':0.1-lOHz)
Tcmpco
pbv nn il'pi;li REaLTTEEMENTS1*
- iV dc. I 59i,
: l5\'dc. t5o/o
PoU'ER SUPPLY REJECTION ( t I 5V dc)
Gain or Offset vs. FSR
Dilfcrential Nonlinearity-i*r rnolirsMAl-*-
Operat ing'lemperaturc-femperaturc
>33ko
>5ko
I 50pF6.000V (Maximum Error,
3pV pk-pk
5ppm/'C
9mA
r 30mA:t 38mA
l00dB
0to +70'C
80dBl/4LSBperVoltAV5
SPEC I Ft CAT| 0 NS'y.'[lfi:#
+ 25"C,rated power supplies unless otherwise noted; specifications formounting card with
same as m0dule unless otherwise noted)
DACI138 on Mounting Card with
Amplifi er/Deglitcher Optrons.
Deglitcher IV { Low Drift 2l4L
(Internal AD542K) i w,/wo Deglitcher
RESOLUTION,BITS
ACCURACY
Integral Nonlinearity
Differential Nonlinearity
Gain and Offset Error (Externally Adiustable)
ANALOGOUTPUT
Unipolar Mode
Bipolar Mode
Voltage Output Range (Pin Selectable)
DIGITAL INPUTS
INPUTCODES
Unipolar Mode
Bipolar Mode
DACll3S Module
l/2LSB max
l/2LSB max
- 2mA to OnA
lmA to + lmA
0ro + 5V,0to + lOV, 15v, a lov
l0ps
8ps
I 75ps
l40ps
l8ps
2VlgsGaln, oftset and glitch-nulling adiustmentsprovided on the mounting card.**1-*-**"--
Voltage Output, Only
Voltage Output, Only
STROBE INPUT
DYNAMIC CHARACTERISTICS
SenlingTimeto li2LSB
Current
Full Scale Step
LSB Step
Voltage
Unipolar (l0V Step)
Bipolar (20V Step)
LSB Step
Slew Rate
TEMPERATURE COEFFICIENTS
(ppm of FSR7"C)
Integral Nonlinearity
Differential Nonlinearity
Gain (Excluding Vpsp)
Offset
Unipolar Mode
Bipolar Mode
STABILITY, LONGTERM
(ppm of FSRJl,000 hrs.)'
Gain (Excluding Vqsil
Offset
NOISE (Include Vp6p; Double for
Bipolar Mode)
OutputCurrent (B'V - l00kHz)
Output Voltage (BrJfl = 0. l-l0Hz)
(a 0V(AlI I'sCode; "ZERO")
(r 5V(MSB = 0Code;"Half Scale")
(rr 10V(Al I0'sCode; "Full Scale")
OutputVoltage(BW = l00kHz)
VOLTAGE COMPLIANCE (Amolifi er
Max Ee5 Allowed for
Rated Accuracy
Initial Eos (Factory Adi.)
E65 Drift
Current Output (pin 69)
Voltage Protection
Source Resistance
Unipolar Mode
Bipolar Mode
Source Capacitance
Voltage (Zour -200Q)
Noise(BrV = 0.1-l0Hz)
Tempco
POWER SUPPLY REQUIREMENTS,
+5Vdc, t5%
tl5Vdc, a5%
80ps
90ps8ps
Mlrs45ps60psl8ps- "- 9Y/p:*
t 0.3
t 0.4
t 0.8
a 0.5
:tl:t0.5 I tO.l
0.5nA rms
4pV pk-pk
6pV pk-pk
9pV pk-pk
30pV rms
t 200pV max
* l00pV
* l0pV/'C
via Internal Schottky Diodes
>33k()
>5ko
l50pF
Voltage Output, Only
40pV rms
,t 50pV
t 5pVi'C
:t 2OpV
* 0. I pV/'C
PO!/ER SUPPLY REJECTION( t l5V dc)
Gain or Offset vs. FSR
Differential Nonlinearitv
+6.000V(MaximumError, +0.024V) i
3pV pk-pk
5ppm/"C l
80dBI/4LSBVolt AV
Characteristic Curves*
0.0(X)1
llls 'l0ps 100Ps lms 10ms
SETTLING TIME
Settling Time (Voltage Output) vs. %'of'Full-Scale'
Error for 10V Ouput Step (0V * +lV)
INPUT CONSIDERATIONS
The DAC113 611138 may be driven by TTL or CMOS as
shown in Figure 2. Note that the TTL input is shown with
inputs for both a direct "totem pole" TTL gate and oPen
collector (or "pull-up") configurations.
2a. TTL Totem Polet2b. Switch or RelaY lnqut"FoB rrL w,rH opEN ""1i..l1"1i"3::.."^. .,...,,
CONVEFTERS HAVE INTERNAL lOKO PULL-UP ON EACH INPUT TO 3.8V.
2. USE SPST SV{ITCH OR RELAY TO GROUND. WHEN SWITCH IS OPEN, THE
INTERNAL lOKO WILL PULL INPUT UP TO 3.8V.
Figure 2. lnput Connections
OUTPUT CONNECTIONS AND GUARDING
The DAC113 6/1138 output connections for various voltage
ranges are shown in Figure 3.
Since an LSB is only 38pV (at 10 volts full scale for the
DAC1138), care must be exercised to properly guard the
current output of the converter from leakage current. Any
connection made to the DAC's current output (pin 69)
should be guarded. Suggested Printed circuit board guarding
is shown in Figure 3. The optional Card-Mounted Assemblies
of the DACl136lll38 have been carefully designed for
optimum guarding and performance.
DAC CONNECT€D FOR IlOV
Figure 3. Output Voltage Connections and Suggested PCBo.o10.001z0.0r
$ o.oorzlo.or0.fi)'lz
1ps 10ps lo0gs 1ms 10ms
SETTLING TIME
Settling Time (Voltage Output) vs. /o-of'Full-Scale-
Enir for 20V Output Step (+l}v + -lv)
%LSB @ 12 BITS
%LSB @ 18 B|TS
%LSB @ 12 B|TS
%LSB @ 18 BrrS
%LSB @ 12 B|TS
%LSB @ r8 B|TS
o.1
--!--- r-+-: -,--i-
:-...'''."' :.::-"'; _ 'i"-t :tt, '':'-- l-;:-:-- -.-" ":; ;..-..-.- - - - ;: ;;^-^- - t -.- --- -.1
10ps 1009s lms
SETTLING TIME
Settling Time (Voltage auQuil vs. o/o'of-Full-Scale-Error for
LSB Steps (Essentially lndependent of Amplifier Used). With
Degtitcher I V, the LSB Step at the Maior Carry Settles as
Fast as the Typical LSB Step, Following the | | W Hold
Period.
---';a- - --.1
GUARD FOIL
DAC CONNECTED FOR 0V ro +5V
DAC CONNECTED FOR OV TO +IOV
DAC CONNECTED FOR !5V
lo lO O O O O o IIssr 6s 53 s2 49 48 47 |
tt:l
cvv
100k20f
OFFSETADJUST
GAIN AND OFFSET ADJUSTMENTS
The gain and offset adjustments are made with external
potentiometers which the user supplies. With the appropriate
digital inputs applied, these potentiometers are adjusted until
the desired output voltage is obtained. The proper connec-
tions for offset and gain are shown in Figure 4. The volt-
meter used to measure the output should be capable of stable
resolution of 1/4LSB in the region of zero and full scale.
Because of the interaction berween offset and gain adjust-
ments, the adjustment procedure described below should be
carefully followed. Offset adjustment affects gain, but gain
adjustment does not affect offset.
DIFFERENTIAL LIN EARITY ADJ USTMENT
Each DAC1136l1138 has been factory calibrated and
tested to achieve the performance indicated in the electrical
specifications. Before attempring recalibration, it is imperative
that the circuit be checked to confirm that all previously de-
scribed precautions have been taken to insure proper applica-
tion at the 16- or 18-bir level. Basically, the DAC is trimmed
by comparing a bit to the sum of all lower bits, and adjusting,
if necessary, for a one LSB positive difference. The top 4
major carries, i.e., MSB minus the sum of bits 2-through-the-
LSB, down through bit 4 minus the sum of bits 5-through-the-
LSB, can be trimmed using the procedure outlined below. A
differential voltmeter capable of 1OOtrrV Full Scale should be
connected to V9g1 of the DAC. This will resolve an LSB
which at 18 bits is 38pV (10V range). A Fluke 895,4, or equiv-
alent is recommended.
1. Bit 4 Trim
a. Set bit inputs to 11110. . . . O.
b. Read the output voltage by nulling rhe voltmeter.
c. Set bit inputs to 11101 . . . . 1.
d. Read voltage by nulling voltmeter. This reading should
be equal to that of step 1b plus 1LSB. Adjust bit 4 if
required (see 84, Figure 6).
2. Bit 3 Trim
a. Set bit inputs to 1110. . . . O.
b. Read output voltage by nulling the voltmeter.
c. Set inputs to 1101 . . . . 1.
d. Read voltage by nulling the voltmeter. This reading
should be equal to that of step 2b plus 1LSB. Adjust
bit 3 if required (see 83, Figure 6).
3. Bit 2 Trim
a. Set bit inputs to 110 . . . . 0.
b. Read output voltage by nulling the voltmerer.
c. Set bit inputs to 101 . . . . 1.
d. Read voltage by nulling vokmeter. This reading should
be equal to that of step 3b plus lLSB. Adjust bit 2
if required (see 82, Figure 6),
4. Bit 1 (MSB) Trim
a. Set bit switches to 100 . . . . O.
b. Read output voltage by nulling the voltmeter.
c. Set bit switches to 011 . . . . 1.
d. Read voltage by nulling voltmerer. This reading should
be equal to that of step 4b plus 1LSB. Adjust bit 1
(MSB) if required (see MSB, Figure 6).
If insufficient range exists on any adjustment, then a separate
adjustrnent for the rygight of bits 5-through-the-LSB (see
Sum B5 -+ LSB, Figure 6) should be performeil. This condition
will probably not occur on bit 2, 3 and 4 but might occur on
the MSB. If adjusfinent of the sum of bits 5-through-the-LSB is
made, the trim procedure for all bits should be repeated. Ob-
viously, since the procedure affects the weight of individual
bits, it affects the overall gain of the DAC. The final step
1136=SHORT ll35=OPEN 1136=56Ok
1138=330k 1138= 150k 1138= 2M
100k100k
207GAIN
ADJUST
tN753A1,",*o
erpoLa;-
OFFSET
TO PIN 34
OR PIN 69rr-
3.01k
50mW00
69 46
DACl 136DAcl138 "^l
NorEs:
+lsvdc -15vdc coMMoN
1. ALL FIXED RESISTORS ARE 5% CARBON COMP, UNLESS OTHERWISE NOTED.2. ALL POTENTIOMETERS ARE 2O.TURN INFINITE RESOLUTTON TYPE.
Figure 4. Gain and Offset Adjustments
For unipolar mode, apply a digital input of all "1's" (com-
plementary binary code for zero ourpur) and adjust the offset
potentiometer until a 0.00000V ourput is obtained (see
Table I). Once the appropriate offset adjustmenr has been
made, apply a digital input of all "0's". Adjust the gain
potentiometer until the plus full scale output is obtained(see Table I).
For bipolar mode, apply a digital input of all "L's" (comple-
mentary offset binary code for minus full scale) and adjust the
offset potentiometer for the proper minus full scale output
voltage (see Table I). Once the appropriate minus full scale
adjustment has been made, apply a digital input of all "0's".
Adjust the gain potentiometer until the plus full scale outpur
shown below is obtained.
3.01k
50mW
RANGE
Unipolar:
OV++lOV
OV--++5V
Bipolar:
-1OV--r+10VAll 11...1
0.ooooov
0.00000v
IDEAL OUTPUT
*'--:-.'DACl138 ; DAC1136All 00...0
:+9.999962V +9.999848V
:+4.99998IY +4.999924V
-lo.ooooov
