DAC1001LCN ,17 V, 9-bit uP compatible, double-buffered D/A converterElectrical Characteristics
Tested at Vcc = 4.75 VDc and 15.75 VDC, TA=25“C, VHEF= 10.000 VDC unles ..
DAC1002LCN ,17 V, 8-bit uP compatible, double-buffered D/A converterElectrical Characteristics
Tested at Vcc = 4.75 VDC and 15.75 VDC, TA=25''C, VREF= 10.000 VDc unle ..
DAC1006LCN ,P Compatible/ Double-Buffered D to A ConvertersPin Description(bits)YSingle Power Supply 5 to 15 VDCDAC1006 10Forleft-DAC1007 9 20justifieddataDAC ..
DAC1008LCN ,P Compatible/ Double-Buffered D to A ConvertersapplicationsYLogic inputs which meet TTL voltage level specs (1.4V(such as digitally controlled gai ..
DAC101S101CIMKX ,10-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail OutputFeaturesn Guaranteed MonotonicityThe DAC101S101 is a full-featured, general purpose 10-bitvoltage-o ..
DAC101S101CIMM ,10-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail OutputPin DescriptionsTSOTMSOP(SOT-23) Symbol DescriptionPin No.Pin No.14 V DAC Analog Output Voltage.OUT ..
DL-3039-011 ,Index Guided AlGalnP Laser DiodeOrdering number: EN5865Red Laser DiodeDL-3039-011Index Guided AlGalnP Laser DiodeOverview Package D ..
DL-3416 , 4-Character 16 Segment Plus Decimal Alphanumeric Intelligent Display®
DL4001 , SURFACE MOUNT RECTIFIERS (REVERSE VOLTAGE: 50 - 1000 V CURRENT: 1.0 A)
DL4002-TP , 1 Amp Glass Passivated Rectifier 50 to 1000 Volts
DL4004-13-F , 1.0A SURFACE MOUNT GLASS PASSIVATED RECTIFIER
DL4004-TP , 1 Amp Glass Passivated Rectifier 50 to 1000 Volts
DAC1000LCJ-DAC1000LCN-DAC1001LCN-DAC1002LCN
17 V, 10-bit uP compatible, double-buffered D/A converter
DAC1000] DAC 1001 / DAC1002/ DAC1006/ DAC1007/DA61008
National _
[ Semiconductor
DAtM000/DAC10ty1/DAC1002/DAtM006/DAC1007/
DAC1008 pLP Compatible,
Double-Buffered D to A Converters
General Description
The DAC1000/1/2 and DAC1006/7/8 are advanced
CMOS/SAK IO-, 9- and 8-bit accurate multiplying DACs
which are designed to interface directly with the 8080, 8048,
8085, Z-80 and other popular microprocessors. These
DACs appear as a memory location or an llO port to the HP
and no interfacing logic is needed.
These devices, combined with an external amplifier and
voltage reierence, can be used as standard D/A converters;
and they are very attractive for multiplying applications
(such as digitally controlled gain blocks) since their linearity
error is essentialiy independent of the voltage reference.
They become equally attractive in audio signal processing
equipment as audio gain controls or as programmable at-
tenuators which marry high quality audio signal processing
to digitally based systems under microprocessor control.
All of these DACs are double buffered. They can load all 10
bits or two 8-bit bytes and the data format can be either right
justified or left justified. The analog section of these DACs is
essentially the same as that of the DAC1020.
The DAC1000 series are the 10-bit members of a family of
microprocessor-compatible DAC's (MICRO-DACTM's). For
applications requiring other resolutions, the DACOBSO series
(8 bits) and the DAC1208 and DAC1230 (12 bits) are avail-
able alternatives.
Accuracy
Part (bits) Pin Deserlptlort
DAC1000 10 Has all
DAC1001 24 logic
D AC1 002 features
DAC1006 10 For left-
DAC1007 20 justified
DAC1008 data
Features
" Uses easy to adjust END POINT specs, NOT BEST
STRAIGHT LINE FIT
u Low power consumption
a Direct interface to all popular microprocessors.
n Integrated thin film on CMOS structure
a Double-buffered, single-buffered or flow through digital
data inputs.
D Loads two 8-bit bytes or a single 10-bit word.
I: Logic inputs which meet TTL voltage level specs (1.4V
logic threshold).
rt Works with t101/ reference-Mull 4-quadrant multiplica-
I: Operates STAND ALONE (without pP) if desired.
a Available in 0.3" standard 20-pin and 0.6" 24-pin pack-
age. ,
:1 Differential non-Iinearity selection available as special
order.
Key Specifications
II Output Current Settling Time 500 ns
a Resolution 10 bits
I! Linearity IO, 9, and 8 bits
(guaranteed over temp.)
u Gain Tempco -0.0003% of FSI°C
I: Low Power Dissipation 20 mW
(including ladder)
a Single Power Supply 5 to 15 VDC
Typical Application
DAC1 006/ 1007/ 1 008
caNInoL I05
lm ulmz
+Vcc " t5Yitt:)
d 3 l 1 " "
. MItRO-Dlt"
20 PIN
u:.oxn_:
M80 Bus
" -oyttit
- . NOTE: FOR DETAILS OF BUS
- CONNECTION SEE SECTION 6.0
TL/H/5688-1
Absolute Maximum RatingS(Notes1&2)
ll MllltarylAerospace specified devices are required. ESD Susceptibility (Note 11) 800V
please contact the National Semiconductor Sales Lead Temp. (Soldering, 10 seconds)
Off1ttttfDlatritnttttrtt for avallablllty and 'rpttttlmtatlontt. DuaI-ln-Line Package (plastic) 260°C
Supply Voltage Nod 17 VDc Dual-in-Une Package (ceramic) 300'C
Voltage at Arty Digital Input Vcc to GND .
Voltage at VREF Input t25V Operating Ratings (Note 1)
Storage Temperature Range -65''C to + 150°C TI',':'),':,',?,', Raga: 'LCN' ffi TMIN S (LAC? Jgpt
. . . - . num ers su IX o
Package Disalpa1lon at a--- 25 C (Note 3) 500 mW P a rt numbers with 'LOJ' ttutrot _ 40°C to + 85°C
DC Voltage Applied to IOUT1 or IOUT2 Part numbers with 'LI' suffix - 55°C to + 125°C
(Note 4) -100 mV to VCC Voltage at Any Digital Input Vcc to GND
Electrical Characteristics
Tested at Vcc = 4.75 VDC and 15.75 VDc. TA---25'C, VREF= 10.000 VDc unless otherwise noted
Vcc = 12VDc l 5% -
Parameter Conditions it', to 15VDC t 5% l/txt-- 5VDtt i 5% Units
Min. Typ. Max; Mln. Typ. Max.
Resolution 10 10 bits
Linearity Error Endpoint adjust only 4,7
TMIN
-t0VsCVREFsc+10V 5
DA01000 and 1006 0.05 0.05 % of FSR
DAC1001 and 1007 0.1 0.1 % of FSR
DAC1002 and 1008 0.2 0.2 %-01FSR
Differential Endpoint adjust only 4,7
Nonlinearity TMIN--10VDAC1000 and 1006 0.1 0.1 % of FSR
DAC1001 and 1007 0.2 0.2 % of FSR
DAC1002 and 1008 0.4 0.4 % of FSR
Monotonicity TMIN -10VKVREFsr+10V 5
DAC1001) and 1006 10 10 bits
DAC1001 and 1007 9 9 bits
DAC1002 and 1008 8 8 bits
Gain Error Using internal Rm
-10Vsi;)mEFsc+10V 5 -1.0 10.3 1.0 -1.0 10.3 1.0 %ofFS
Gain Error Tempco TMIN Using internal Re, 9 -0.0003 -0.00t -0.0006 --0.002 M, of FSPG
Power Supply All digital inputs
Rejection latched high
Vcc = 1 4.5V to 15.5V 0.003 0.008 % FSRIV
11.5V to 12.5V 0.004 0.010 % FSR/V
4.75V to 5.25V 0.033 0.10 % FSR/V
Reference Input
Resistance 10 15 20 10 15 20 kn
Output Feedthrough VREF = 20Vp-p, f-- 100 kHz
Error All data inputs
latched low
D Package 130 130 mVp.p
N Package 90 90 mVp.p
Output 'OUT1 All data inputs 60 60 pF
Capacitance IOUTZ latched low 250 250 pF
IOUT1 All data inputs 250 250 pF
'OUT2 latched high 60 60 pF
Supply Current Drain TMIN g TA s; TMAX 6 0.5 3.5 0.5 3.5 mA
800l0VO/l00lOVCl/QOOLOVG/ZOOLOVG/ lOOLOVG/OOOLOVG
DAC1000/DAC1001IDAC1002/DAC1006/DAC1007/DAC1008
Electrical Characteristics
Tested at Vcc --.-' 4.75 VDC and 15.75 VDC, TA---25'C, VREF= 10.000 VDC unless otherwise noted (Continued)
Vcc = 121ftttt i 6% =
Parameter Conditions :3; to 1 5VDc i " Vet: SVDc i 5% Unite
Mln. Typ. Max. Mln. Typ. Max.
Output Leakage TMIN S TAS TMAX 6
Current IOUT1 All data inputs
latched low 10 200 200 nA
IOUT2 All data inputs
latched high 200 200 nA
Digital Input TMIN S TA S TMAX 6
Voltages Low level
LJ suffix 0.8 0.6 VDC
LCJ, LCN suffix 0.8, 0.8 0.7, 0.8 VDC
High level (all parts) 2.0 2.0 hx:
Digital Input TMINSTASTMAX 6
Currents Digital inputs <0.8V - 40 - 150 _ 40 - 150 Moc
Digital inputs > 2.0V 1.0 + 10 1.0 + 10 P-ADC
Current Settling ts " = 0V, VIH = 5V 500 500 ns
Write and XFER tw VIL = 0V, VIH = 5V,
Pulse Width TA = 25°C _ 8 150 60 320 200 ns
TMIN STASTMAX 9 320 100 500 250 ns
Data Set Up Time tDs kk-- 0V, VgH = 5V,
TA = 25''C 9 150 80 320 170 ns
TMINSTASTMAX 320 120 500 250 ns
Data Hold Time tDH Vic---- ov, VIH = 5V
TA = 25''C 9 200 100 320 220 ns
TMlNSTASTMAx 250 120 500 320 ns
Control Set Up tcs " = 0V, " = 5V,
Time TA = 25°C 9 150 60 320 180 ns
TMINSTASTMAX 320 100 500 260 ns
Control Hold Time tCH " == 0V, VIH = 5V,
TA = 25°C 9 1 0 O 1 0 0 ns
TMINSTASTMAX 10 0 10 0 ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC elecu'icej spethticatems do not apply when operating
the device beyond its spocmed operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise tspecified.
Note 3: This 500 mW spkrfication applies for all packages. The low intrinsic power dissipation of this part (and the tact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking.
Note 4: For current switching applications, both 'oun end loum must go to ground or the "Vimal Ground" of an operational amplifier. The Ilnearlty mat is
degraded by approximately vos + VREF. For example, if VR5F=10Vthen a t mV onset. Vos, on Iour, or lou'rz will introduce an additional 0.01 % lineatity error.
Note 5: Guaranteed at VREF= i 10 VDC and VHEF: kt VDC.
Note 6: TMIN=0‘C and TW=70"C tor "LCN'' suffix parts.
TMlN= -4trc end TMAx=85°C for "LCJ" suffix parts.
Tum = 55'C and TMAX =125''C for "LI" suffix parts.
Note T.. The unit "FSR" stands for "Full Scale Range." "Unearity Error" and “Power Supply Rejection" specs are based on this unit to eliminate dependence on a
particular VREF value and to indicate the true pertormaneo of the part The "Linaarity Error" 'tpecifeatiott of the DACIOOO is “0.05% of FSR (MAX)." This
guarantees that after performing a zero and fur scale ad'lustrmmt (See Sectitms 2.5 and 2.6). the plot of the 1024 analog voltage outputs " each be within
0.05% XVREF of a straight line which passes through zero and full scale.
Note & This specitieatitrn implies the! all parts are guaranteed to operate with a write pulse or trensfat pulse width (M) of 320 ns. A typical part will operate with tw
of onty 100 ms. The entire write pulse must occur within the valid data interval for the trpoeitiad tw, ins. ttm, and ts to apply.
Note 9: Guaranteed by design but not tested.
Note Ittt A 200 nA leakage cmant with Rm--20k end VREF-10V corresponds to a zero erroc of(20oxt0-9x2ttrt1ty3)rtttn:-10 which Is 0.04% of FS.
Note 11: Human bot model, 100 pF discharged through a 1.5 kn resistor.
Switching Waveforms
M. Imuamz
MTh .113
'OUT1 F 'tttttt
Mltt 50%
lr-_-utr-"---! ttral---
"m 5M< I ye'-'
'ss SETTLE0 T0
:t‘hLSB
Typical Performance Characteristics
Errors vs. Supply Voltage
Errors vs. Temperature
TLfH/5688-2
Write Width, tw
VIM: W
500 mm = av TO "
if. ace
-55-35-15 5 " " 55 35105125
AMBIENT TEMPERNURE ('C)
Data Hold Time, to"
= " Til "
Vac =mr
ll =1ov
= W" CC
CONTROL SETUP YIHE. YDH (m)
Hi5 -35-15 s 25 " 65 " 105 l25
ta, AMBIE’" TEMPERATURE ('0)
Dlgltal Input Threshold
.1; g om
3 , 0.025 A ununm mun
E g 0.000
g 3 4.02:
5 E a um mm
p, E -thtN0
o s n " "tess-ss-ts s ts u u " mm
sumv mm: m mm mum mnmuns re)
Control Setup Tlme, tes Data Setup Time,
i" VIIIL=W .iii.' m =W
T, " 'ttms-WNW a " um
tl “ tl 4tn
.. m --10 " 3m
ill Vcc=wv E
" m a' m
g F..'
3 m , IN
-65-M-ts s 25 " " IS mslzs HU-N-ts ' ts 45 as as 105125
AIBIEIT IEIPEIWUM m m. mum Impennun: (T)
Digital Threshold
vs. Supply Voltage
" g 1 t
5 u lum-c it' "
u s w IS -M-M-
mm“ mum: m: m
vs. Temperature
" 5 " " $5
TEIPEMTIJREPC)
" 105 Its
TL/H/5688-3
800LOVG/lOOlOVG/SOOI.OVO/ZOOl-OVO/lOOlOVG/OOOLOVO
DAC1000/DAC1001IDAC1002/DAC1006lDAC1007/DAC1008
Block and Connection Diagrams
DAC1OOD/ 1001/ 1002 (24-Pln Parts)
(rm) " "
um) um "
(HSI) nlg
(us) run
DAC1006/ 1007/ 1008 (20-Pln Parts)
In 2nd
BYTE BYTE
STRDBE STMIE
BEtrt8TElt
XFEH STHOBE
t t 4 '
ct an ma am 1/
CONTROL L030!)
_ " 2V“;
. . 13 ,
. . " nun
10-"! l m : mm um
mm mum: uummmn
urcu : il"" 'o""'"!
o q .--lt"
A M, ggi, "
mm man M n mc tr v“
um LL I --"rto
" " 5 " 4 2 "
E? rm W rm mn/ w "
t VREF
USE DAC1006/1007/1008
FOR LEFT JUSTIFIED DATA
TL/H/5688-S
DAtM000M0001002
(24-Pln Parts)
DuaI-In-Llne Package
wif--,
am "Wt--
unannoun—
tlu---
IISI] ttle---
.0...‘
MC IOM,
1001. tttot
- ND M8)
- VIEF
--ltutt
- le’z
TOP VIEW
TL/H/6688-4
DAtM00tUt00rM008
(zo-Pln Parts)
DuaI-ln-Llne Package
Rg..--,
um "FT---
gm..-,
(IS!) th--
'Ito--
" --ittt
" "-0ld
u -th3
" -0ip
u --0lt
" -thttM8)
" --lim
" ""'"httr
" -lotm
ll -roiltt
TUH/6B88-28
Top View
See Ordering Information
DAC1000/1001M002-Slmple Hookup for a “QuiCk Look"
'A TOTAL OF 10
INPUT SWITCHES
a 1K RESISTORS TLfHf5688-6
Notes:
1. For VREF= - 10.240 Voc the output voltage steps are approximately 10 mV each.
2. Operation is set up mr Mw thrtmgtr-eto latching of digital input data.
3. Single point ground is strongly recommended.
DAC1006/ 1007/ 1008-Simple Hookup for a "Quick Look"
SW1 “5ch , + 15Vnc
h-O‘F Vou‘l
= m ts" "
"A TOTAL OF "
INPUT SWITCHES
& 1K RESISTORS
-VIIEF
TL/HISBBB-7
Notes:
1. For Vngp= -10.240 VDc the output voltage steps are approximately 10 mV each.
2. SW1 is a normaly closed odtch. While SW1 is closed. the DAC rettster is latched and new data
can be loaded into the input latch via the 10 SW2 switches.
When SW1 is momentarily opened the new data is transiened from me input latch to the DAC register and is latched when SW1 again closes.
800LOVO/ £OOI-OVG/90010VCII ZOULOVG/ lOOI-OVG/ OOOlOVCl
DAC1000/DAC1001IDAC1002/DAC1006/DAC1007/DAC1008
1.0 DEFINITION OF PACKAGE PINOUTS
1.1 Control Signals (All control signals are level actuated.)
E: Chip Select - active low, it will enable W (DAC1003-
1008) or WR1 (DAC1000-1002).
WA or Wrti. Write - The active low WT! (or WFT1 -
DAC1000-1002) is used to load the digital data bits (DI) into
the input latch. The data in the input latch is latched when
Mm (or Wth) is high. The 10-bit input latch is split into two
latches; one holds 8 bits and the other holds 2 bits. The
Byttr1/Byte2 control pin is used to select both input latches
when Byte1/Byte2=1 or to overwrite the 2-bit input latch
when in the low state.
Wits Extra Write (DACl 000-IM2) - The active low Wma
is used to load the data from the input latch to the DAC
register while YFER is low. The data in the DAC register is
latched when WR2 is high.
Byte1/Byte2: Byte Sequence Control - When this control
is high, all ten locations of the input latch are enabled. When
low, only two locations of the input latch are enabled and
these two locations are overwritten on the second byte
write. On the DAC1006, 1007, and 1008, the Byte1/Byte2
must be low to transfer the 10-bit data in the input latch to
the DAC register.
XFER: Transfer Control Signal, active low - This signal, in
combination with others, is used to transfer the 10-bit data
which is available in the input latch to the DAC register -
see timing diagrams.
Lu/ra.. Left Justify/Right Justify fDAC1000-1002) - When
LU/AIT is high the part is set up for left justified (fractional)
data format. (DAG1006-1008 have this done internally.)
When LJ/R_J is low, the part is set up for right justified (inte-
ger) data.
1.2 Other Pin Functions
DI. (I= 0 to 9): Digital Inputs - Dlo is the least significant bit
(LSB) and Dig is the most significant bit (MSB).
tour: DAC Current Output 1 - '0UT1 is a maximum for a
digital input code of all Is and is zero for a digital input code
of all Os.
Iourat DAC Current Output 2 - lour2 is a constant minus
Iourl, or
1023 VREF
1024 R
where H a 15 kn.
loun + |OUT2=
a. End Point Test After Zero and FS Ad].
h L53 ERROR
ANAlOG OUTPUT
IDEAL RESPONSE
DIGITAL SNPUT
Rpg: Feedback Resistor - This is provided on the IC chip
for use as the shunt feedback resistor when an external op
amp is used to provide an output voltage for the DAC. This
on-chip resistor should always be used (not an external re-
sistor) because it matches the resistors used in the on-chip
R-2R ladder and tracks these resistors over temperature.
VREF: Reference Voltage Input - This is the connection for
the external precision voltage source which drives the R-2R
ladder. VREF can range from - 10 to + 10 volts. This is also
the analog voltage input for a 4-quadrant multiplying DAC
application.
Vcci Digital Supply Voltage - This is the power supply pin
for the part. Vcc can be from + 5 to + 15 VDC. Operation is
optimum for +15V. The input threshold voltages are nearly
independent of Vcc, (See Typical Performance Characteris-
tics and Description in Section 3.0, T2L compatible logic
inputs.)
GND: Ground - the ground pin for the part.
1.3 Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example. the DACtOOO
has 210 or 1024 steps and therefore has 10-bit resolution.
Linearity Error: Linearity error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer tpharatMristitt. It is measured after adjusting
for zero and full-scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.
National's linearity test (a) and the "best straight line" test
(b) used by other suppliers are illustrated below. The "best
straight line" requires a special zero and FS adjustment for
each part, which is almost impossible for user to determine.
The "end point test" uses a standard zero and FS adjust-
ment procedure and is a much more stringent test for DAC
linearity.
Power Supply Sensltlvlty: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
tull-scale output (which is the worst case).
b. Beat Straight Line
th LS8 ERROR BAND
ACTUAL
ANALOG OUTPUT
DIGITAL INPUT
TL/H/5688-6
Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within 19/2 LSB of
the final output value. Full-scale settling time requires a zero
to tull-scale or tull-scale to zero output change.
Full-Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC1000 series, tull-scale is Vmr-1 LSB.
For VREF= - 10V and unipolar operation, VFULL-
SCALE=10.0000V -9.8mV--9.9902V. Full-scale error is
adjustable to zero.
Monotonlclty: It the output of a DAC increases for increas-
ing digital input code, then the DAC is monotonic. A 10-bit
DAC with 10-bit monotonicity will produce an increasing an-
alog output when all 10 digital inputs are exercised. A 10-bit
DAC with 9-bit monotonicity will be monotonic when only
the most significant 9 bits are exercised. Similarly, 8-bit
monotonicity is guaranteed when only the most signiMant 8
bits are exercised.
2.0 DOUBLE SUFFERING
These DACs are double-buftered, microprocessor compati-
ble versions of the DACI 020 10-bit multiplying DAC. The
addition of the buffers for the digital input data not only al-
lows for storage of this data, but also provides a way to
assemble the 10-bit input data word from two write cycles
when using an 8-bit data bus. Thus, the next data update for
the DAC output can be made with the complete new set of
1o-bit data. Further, the double buffering allows many DACs
in a system to store current data and also the next data. The
updating of the new data for each DAC is also not time
critical. When all DACs are updated, a common strobe sig-
nal can then be used to cause all DACs to switch to their
new analog output levels.
+ Iltt
3.0 TTI. COMPATIBLE LOGIC INPUTS
To guarantee TTL voltage compatibility of the logic inputs, a
novel bipolar (NPN) regulator circuit is used. This makes the
input logic thresholds equal to the forward drop of two di-
odes (and also matches the temperature variation) as oc-
curs naturally in TTL. The basic circuit is shown in Figure t.
A curve of digital input threshold as a function of power
supply voltage is shown in the Typical Performance Charac-
teristics section.
4.0 APPLICATION HINTS
The DC stability of the VREF source is the most important
factor to maintain accuracy of the DAC over time and tem-
perature changes. A good single point ground for the analog
signals is next in importance.
These MICRO-DAC converters are CMOS products and
reasonable care should be exercised in handling them prior
to final mounting on a PC board. The digital inputs are pro-
tected, but permanent damage may occur it the part is sub-
iected to high electrostatic fields. Store unused parts in con-
ductive foam or anti-static rails.
4.1 Power Supply Sequencing lk Decoupllng
Some IC amplifiers draw excessive current from the Analog
inputs to v- when the supplies are first turned on. To pre-
vent damage to the DAC - an external Schottky diode con-
nected from IOUT1 or knmt to ground may be required to
prevent destructive currents in '0UT1 or Iour2. If an LM741
or LF356 is used - these diodes are not required.
The standard power supply decoupling capacitors which are
used for the op amp are adequate for the DAC.
(3 t + VTHH)
A Vans
"-'" (TO 0mm mmsl
(29+ "ttttl
. ' Yo:
,'' " " dmassuum =20
TL/H/5688-9
FIGURE 1. Basic Logic Threshold Loop
800lOVOMOOLOVG/SOOIOVG/ZOOlOVG/ lOOLOVG/OOOI-OVG
DAC1000/DAC1001IDAC1002/DAC1006/DAC1007/DAC1008
4.2 Op Amp Blas Current a. Input Leads
The op amp bias current (I3) CAN CAUSE DC ERRORS. Bl-
FEITM op amps have very low bias current, and therefore
the error introduced is negligible. BI-FET op amps are
strongly recommended tor these DACs.
The distance from the Iour, pin of the DAC to the inverting
input of the op amp should be kept as short as possible to
prevent inadvertent noise pickup.
5.0 ANALOG APPLICATIONS
The analog section of these DACs uses an R-2R ladder
which can be operated both in the current switching mode
and in the voltage switching mode.
The major product changes (compared with the DAC1020)
have been made in the digital functioning of the DAC. The
analog functioning is reviewed here for completeness. For
additional analog applications, such as multipliers, attenua-
tom, digitally controlled amplifiers and low frequency sine
wave oscillators, refer to the DAC1020 data sheet. Some
basic circuit ideas are presented in this section in addition to
complete applications circuits.
5.1 Operation In Current Swltchlng Mode
The analog circuitry, Figure 2, consists of a silioon-chromi-
um (Si-Cr) thin film R-2R ladder which is deposited on the
surface oxide of the monolithic chip. As a result; there is no
parasitic diode connected to the VREF pin as would exist it
diffused resistors were used. The reference voltage input
(VREF) can therefore range from -10V to +10V.
The digital input code to the DAC simply controls tho posi-
tion of the SPDT current switches, SWO to SW9. A logical 1
digital input causes the current switch to steer the avail-
able ladder current to the 'OUTt output pin. These MOS
switches operate in the current mode with a small voltage
drop across them and can therefore switch currents of ei-
ther polarity. This is tho basis for the 4-quadrant multiplying
feature of this DAC.
5.1.1 Providing a Unlpotar Output Voltage with the
mm In the Current Switching Mode
A voltage output is provided by making use of an external
op amp as a current-to-voltage converter. The idea is to use
the internal feedback resistor, RFB, from the output of the
op amp to the inverting I--) input. Now, when current is
entered at this inverting input, the feedback action of the op
amp keeps that input at ground potential. This causes the
applied input current to be diverted to the feedback resistor.
The output voltage of the op amp is forced to a voltage
given by:
VOUT = -(louTtxRFB)
Notice that the sign of the output voltage depends on the
direction of current flow through the feedback resistor.
In current switching mode applications, both current output
pins (lour1 and Ioura) should be operated at 0 VDC. This is
accomplished as shown in Figure 3. The capacitor, ce, is
used to compensate for the output capacitance of the DAC
and the input capacitance of the op amp. The required feed-
back resistor, RFB, is available on the chip (one end is inter-
nally tied to Iorm) and must be used since an external
resistor will not provide the needed matching and tempera-
ture tracking. This circuit can therefore be simplified as
DIGITAL INPUT CODE
(“33) ll m; an. o o e e on ma Mil)
tt a ""P'"
2 VnEF - - - - -
m " " "
o o e e o L
sm tleg SW1 SW1 1, II
, " 2 ,"
O IOUH
R 3 15 Mt
FIGURE 2. Current Mode Swltchlng
{INTERNAU in Ittttt 1
van "p,',"
"VIRTUAL 8600M!"
H W Whit) o---" I--.
tm, 't cc
"tter o- mcnu-nac Dt Oh -o Your = -tlotmx tttti)
--nr"tj,
FIGURE 3. Convertlng tour to Vom- LF356 22 co 3
OP AMP cc pF n, ts Ms TUH/m_w
LF351 24 co 4
LF357 10 2.4K 1.5
shown in Figure 4, where the sign of the reference voltage
has been changed to provide a positive output voltage. Note
that the output current, lotm, now flows through the RFB
5.1.2 providing a Bipolar Output Voltage with the
DAC in the Current Switching Mode
The addition of a second op amp to the circuit of Figure 4
can be used to generate a bipolar output voltage from a
fixed reference voltage Figure 5. This, in effect. gives sign
significance to the MSB of the digital input word to allow two
quadrant multiplication of the reference voltage. The polarity
of the reference can also be reversed to realize the full tour-
quadrant multiplication.
The applied digital word is offset binary which includes a
code to output zero volts without the need of a large valued
resistor common to existing bipolar multiplying DAC circuits.
Offset binary code can be derived from 2's complement
data (most common for signed processor arithmetic) by in-
vening the state of the MSB in either software or hardware.
After doing this the output then responds in accordance to
the following expression:
where VREF can be positive or negative and D is the signed
decimal equivalent of the 2's complement processor data.
(--512scDe; +511 or 1MOOOOOOOSDSO111111111). If the
applied digital input is interpreted as the decimal equivalent
of a true binary word, VOUT can be found by:
VOZVREF( 512 )
IMth this configuration, only the offset voltage of amplifier 1
need be nulled to preserve linearity of the DAC. The offset
voltage error of the second op amp has no effect on lineari-
ty. It presents a constant output voltage error and should be
nulled only if absolute accuracy is needed. Another advan-
tage of this configuration is that the values of the external
resistors required do not have to match the value of the
internal DAC resistors; they need only to match and temper-
ature track each other.
A thin film 4 resistor network available from Beckman Instru-
ments, Inc. (part no. 694-3-R10K-D) is ideally suited for this
application. Two of the four available 10 kn resistor can be
paralleled to form R in Figure 5 and the other two can be
used separately as the resistors labeled 2R.
0SDS1023
D Operation is summarized in the table below:
Vo = VREF XE
Applied
2’s Comp. 2's Comp. Applied True Binary Vom-
(Decimal) (Binary) Digital Input (Decimal) + VREF -VREF
+511 0111111111 1111111111 1023 VREF-ILSB -lVmrl+1LSB
+ 256 0100000000 1 100000000 768 VREF/2 - IVREFIIZ
0 0000000000 1000000000 512 0 0
--1 1111111111 0111111111 511 -ILSB +1LSB
-256 1 100000000 0100000000 256 w VREF/z + IVREFIIZ
- 512 1000000000 0000000000 0 -VREF + IVREFI
with: 1 LSB Jn.itl
512 m: -
(+ 15 vac)
- wtEro= mchAc -4"ttg,
- 0 m: q Vout < Hm GEE)
FIGURE 4. Providing a Unipolar Output Voltage
[+15V) "
His ll V It
*8ttrtt
TLfH/5688-11
FIGURE 5. Providing a Bipolar Output Voltage with the DAC in the Current Switching Mode
QOOLOVG/ [.0010VO/ QOOLOVG/ ZOOl-OVG/ lOOlOVG/ OOOLOVO
DAC1000/DAC1001/DAC1002/DAC1006/DAC1007/DAC1008
5.2 Analog Operation m the Voltage Switching Mode Notice that this is unipolar operation since all voltages are
Some useful application circuits result if the R-2R ladder is positive. A bipolar output voltage can be obtained by using a
operated in the voltage switching mode. There are two very single op amp as shown in Figure tth For a digital input
important things to remember when using the DAC in the Coda of all zeros, the output voltage from the VREF pin is
voltage mode. The reference voltage (+V) must always be zero volts. The external op amp now has a single input of
positive since there are parasitic diodes to ground on the +V and is operating with a gain of -1 to this input. Thty
Ioun pin which would tum on if the reference voltage went output of the op amp therefore will be at ‘V for a digital
negative. To maintain a degradation of linearity less than input ot all 29’03- As the digital ctxie increases, the output
io.oos%, keep +v s 3 ch and Vcc at least 10V more voltage at the VREF pin inCreatttttt.
positive than +V. Figums6and 7show these errors for the Notice that the gain of the op amp to voltages which are
voltage switching mode. This operation appears unusual, applied to the (+) input Is +2 and the gain to voltages
since a reference voltage (+V) is applied to the Iou-n pin which are applied to the input resistor, R, is -1. The output
and the voltage output is the VREF pin. This basic idea is voltage of the op amp depends on both of these inputs and
shown in Figure 8. is given by:
This VOUT range can be scaled by use of a non-inverting VOUT=(+V) (--1)+VRErt+ 2)
gain stage as shown in Figure a
+.1 +.1
..... A uumm mun aunaam um
5 +35 F +35
ii''; E
= o g o
iii A am am ir, em mo:
5 -35 a -.35
8tt =15v " "
uizaissrn 0246!")121413
"WINE mm: " Woe) sumv vomas. vcc (vac)
FIGURE 6 FIGURE T
DIGITAL INPUT CODE
Dlyo o o o . DH Din Mil)
"ir'' mcno-nnc
C' VOUT
TLIH/5688-IZ
FIGURE 9. Amplifying the Voltage Mode Output (Single Supply Operation)
(+15Vnc)
“901m"
-t.0tm < vour < 2.5m (2%)
"Vnsr" menu»: it LF356 --ohm
o-AAN -
- it a steam AND smuua
- " --MN-- nn: 31.3,.53:
( +2500 Vac) tNt
(Lima)
. FIGURE 10. Providing a Bipolar Output Voltage with a Single Op Amp
'tt ”1500 Vucl " =133x
---ANV-
"8tttF'' "tttMW: -omn
unit -limt; A Vour q mm (3%)
Nr." "-' sumac mo smum
TIME e zpssc
o < Vim: A +2.5 Vnc (%)
TLfH/6688-13
FIGURE 11. Increasing the Output Voltage Swing
The output voltage swing can be expanded by adding 2
resistors to Figure 10 as shown in Figure ft. These added
resistors are used to attenuate the + V voltage. Tho overall
gain, Avi-), from the +V terminal to the output of the op
amp determines the most negative output voltage, -4(+ V)
(when the VREF voltage at the + input of the op amp is
zero) with the component values shown. The complete dy-
namitt range of VOUT is provided by the gain from the (+)
input of the op amp. As the voltage at the l/REF pin ranges
from 0V to +V(1023/1024) the output of the op amp will
range from -10 VDC to +10V (1023/1024) when using a
+ V voltage of + 2.500 VDC. The 2.5 Voc reference voltage
can be easily developed by using the LM336 zener which
can be biased through the RFB internal resistor, connected
to Vcc.
5.3 Op Amp Vos Adjust (Zero Adjust) for Current
Switching Mode
Proper operation of the ladder requires that all of the 2R
legs always go to exactly 0 VDC (ground). Therefore offset
voltage, vos, of the external op amp cannot be tolerated as
every millivolt of vos will introduce 0.01% of added linearity
error. At first this seems unusually sensitive, until it becomes
clear the 1 mV is 0.01% of the 10V reference! High resolu-
tion converters of high accuracy require attention to every
detail in an application to achieve the available performance
which is inherent in the part. To prevent this source of error,
the Vos of the op amp has to be initially zeroed. This is the
“zero adjust" of the DAC calibration sequence and should
be done first.
It the vos is to be adjusted there are a few points to consid-
er. Note that no “dc balancing" resistance should be used
in the grounded positive input lead of the op amp. This re-
sistance and the input current of the op amp can also create
errors. The low input biasing current of the Bl-FET op amps
makes them ideal for use in DAC current to voltage applica-
tions. The Vos of the op amp should be adjusted with a
digital input of all zeros to force IOUT=0 mA. A 1 kn resistor
can be temporarily connected from the inverting input to
ground to provide a dc gain of approximately 15 to the vos
of the op amp and make the zeroing easier to sense.
5.4 Full-Scale Adlust
The tull-scale adjust procedure depends on the application
circuit and whether the DAG is operated in the current
switching mode or in the voltage switching mode, Tech-
niques are given below for all of the possible application
circuits.
5.4.1 Current Switching with Unipolar Output Voltage
After doing a ”zero adjust," set all of the digital input levels
HIGH and adjust the magnitude of VREF tor
. 1023
VOUT- - (ideal VREF) 1024
This completes the DAC calibration.
BOOLOVG/LOOlOVO/QOOlOVG/ZOOLOVG/WOlOVCl/OOOLOVG
DAC1000/DAC1001lDAC1002/DAC1006/DAC1007/DAC1008
5.4.2 Current Switching with Bipolar Output Voltage
The circuit of Figure 12 shows the 3 adjustments needed.
The first step is to set all of the digital inputs LOW (to force
Iour1 to 0) and then trim "zero adj." for zero volts at the
inverting input (pin 2) of 0A1. Next, with a code of all zeros
still applied, adiust "-FS adj.", the reference voltage, for
VOUT= l I(ideal VREF)I. The sign of the output voltage will
be opposite that of the applied reference,
Finally, set all of the digital inputs HIGH and adjust "+ FS
adj." for VOUT=VREF (511/512). The sign of the output at
this time will be the same as that of the reference voltage.
The addition of the 2000 resistor in series with the VnEF pin
of the DAC is to force the circuit gain error from the DAC to
be negative. This insures that adding resistance to Rm, with
the soon pot, will always compensate the gain error of the
5.4.3 Voltage Switching with a Unipolar Output Voltage
Refer to the circuit of Figure 13 and set all digital inputs
LOW. Trim the "zero adi." for VOUT=° V0611 mV. Then
set all digital inputs HIGH and trim the "FS Adi." tor:
R1)1023
v == +v I+-' -.._.
OUT==( I R2/1024
5.4.4 Voltage Switching with a Blpolar Output Voltage
Refer to Figure 14 and set all digital inputs LOW. Trim the
" -FS Adj." for VOUT= - 2.5 hoo Then set all digital inputs
HIGH and trim the " + FS Adj." tor VOUT= +2.5 (511/512)
VDc- Test the zero by setting the MS digital input HIGH and
all the rest LOW. Adjust vos of amp #3, if necessary, and
recheck the full-scale values.
(+55 AN)
+158 Ne,
H: AN)
t8ttr T
O Iaun
NO Aa; m
"-NN- VREF
mcno-oAc
"pr 1m:
+ ho VUUT
-V SV g+V 'a
REF OUT REF (512
FIGURE 12. Full Scale Adlust - Current Switehlng with Bipolar Output Voltage
REF MICRO-DAC
I F8 AN.
(+2.5novnci
woe A vour < 2.5m (1 490$)
TL/H/5688-1 4
FIGURE 13. Full Scale Adjust - Voltage Switching with a Unipolar Output Voltage
+FS AN.
IIERO-DIC
(2.53Vnc)
-FS AN.
IP MATCH TO 0.01%
-ANV-o--MN
15K 15K
3 hovour
-.2.58 < VouT < 2.56%) v
TlJH/5888-15
FIGURE t4. Voltage Switching with a Bipolar Output Voltage
6.0 DIGITAL CONTROL DESCRIPTION
The DAC1000 series of products can be used in a wide
variety of operating modes. Most of the options are shown
in Table 1. Also shown in this table are the section numbers
of this data sheet where each of the operating modes is
discussed. For example, if your main interest in interfacing
to a p.P with an 8-bit data bus you will be directed to Section
The first consideration is "will the DAC be interfaced to a pP
with an 8-bit or a 16-bit data bus or used in the stand-alone
mode?' For the 8-bit data bus, a second selection is made
on how the 2nd digital data buffer (the DAC Latch) is updat-
ed by a transter from the Ist digital data buffer (the Input
Latch). Three options are provided: 1) an automatic transfer
when the 2nd data byte is written to the DAC, 2) a transfer
which is under the control of the pP and can include more
than one DAC in a simultaneous transfer, or 3) a transfer
which is under the controi of external logic. Further, the data
format can be either left iustitied or right iustititsd.
When interfacing to a p.P with a 16-bit data bus only two
selections are available: I) operating the DAC with a single
digital data butter (the transfer of one DAC does not have to
be synchronized with any other DACs in the system), or 2)
operating with a double digital data buffer for simultaneous
transfer. or updating, of more than one DAG.
For operating without a HP in the stand alone mode, three
options are provided: 1) using only a single digital data buff-
er, 2) using both digital data buffers - "double buffered." or
3) allowing the input digital data to "flow through" to provide
the analog output without the use of any data latches.
To reduce the required reading, only the applicable sections
of 6.1 through 6.4 need be considered.
6.1 Intertaclng to an tVBlt Data Bus
Transferring 10 bits of data over an 8-bit bus requires two
write cycles and provides four possible combinations which
depend upon two basic data format and protocol decisions:
l. Is the data to be left Mrtified (considered as fractional
binary data with the binary point to the left) or right iusti-
fied (considered as binary weighted data with the binary
point to the right)?
2. Which byte will be transferred first, the most significant
byte (MS byte) or the least significant byte (LS byte)?
800LOVO/tOOlGVO/QOOl-OVCl/ZOOLOVG/ lOOLOVO/OOOIOVG
Table 1
Operating Mode Automatic Transfer M' Control Transfer External Transfer
Figure No. Figure No. Figure No.
Data Bus Setttittn (24-Pin) (20-Pm) Section (24-Pln) (20-Pin) sum" (24-Pln) (20-Pln)
B-Bit Data Bus (6.1.0)
Right Justified (6.1.1) 6.2.1 16 6.2.2 16 6.2.3 16
Left Justified (6.1.2) 6.2.1 17 18 6.2.2 17 18 6.2.3 17 18
1 6-Bit Data Bus (6.3.0) Single Buffered Double Buffered Flow Through
6.3.1 19 20 6.3.2 19 20 Not Applicable
Stand Alone (6.4.0) Single Buffered Double Buffered Flow Through
6.4.1 19 20 6.4.2 19 20 6.4.3 19 NA
DAC1000/DAC1001IDAC1002/DAC1006/DAC1007IDAC1008
These data possibilities are shown in Figure M, Note that 6.1.2 For Left Justified Data
the justification of data depends on how the 10-bit data For applications which require lettjustified data, DAC1006-
word is located within the 16-bit data source (CPU) register. 1008 (20-pin parts) can be used. A simplified logic diagram
In either case, there is a surplus of 6 biteand these are which shows the external connections to the data bus and
shown as "don't care'' terms Cx") in this figure. the internal functions of both of the data buffer registers
All of these DACs load 10 bits on the 1st write cycle. A (Input Latch and DAC Register) is shown in Figure M.
particular set of 2 bits is then overwritten on the 2nd write These parts require the MS or Hi Byte data group to be
cycle, depending on the justification of the data. This "F. transferred on the 1st write cycle.
quires the tst write cycle to contain the LS or L0 Byte data
group for all right justified data options. For all left iustified 6.2 Controlling Data Transfer for an tVBlt Data Bus
data options, the 1st write cycle must contain the MS or Hi Three operating modes are possible for controlling the
Byte data group. transfer of data from the Input Latch to the DAC Register,
where it will update the analog output voltage. The simplest
6.1.1ProvldlngtorOptlonalDataFormat is the automatic transfer mode, which causes the data
The DAC1000/1/2 (24-pin parts) can be used for either transfer to occur at the time of the 2nd write cycle. This is
data formatting by tying tho LJ/FTJ pin either high or low, recommended when the exacttiming of the changes of the
respectively. A simplified logic diagram which shows the ex- DAC analog output are not critical. This typically happens
ternal connections to the data bus and the internal functions where each DAC is operating individually in a system and
of both of the data buffer registers (Input Latch and DAC the analog updating of one DAC is not required to be syn-
Register) is shown in Figure M for the right justified data chronized to any other DAC. For synchronized DAC updat-
operation. Figure 17is for lettjustitied data. ing, two options are provided: pP control via a common
XFER strobe or external update timing control via an exter-
nal strobe. The details of these options are now shown.
r um m: l Mir m: I
I I I-l I I I I
am sum: mum uouxne 10-!" um um
I I I I I I I I
l mm: 1 Lam: l
an immune: um LEI x , , x , x
F------ I m m! -nl
x x , ll x x IS! "TT'T" us
FIGURE 15. Fitting a 10-Blt Data Word Into " Available Blt Locations
DAC1000/ 1001 / 1002 (24-Pln Parts)
It m usu
iit ' ( t iii: -t, a.'-'hV
I - B LATCH n - n tt
\ " ' n tt “HI! 0 -
L " , II n m - to
" D ll a mum: n - cumin
M" n M" il n tr mrcm
mun: , ' INPUT -
L k um ' n n
f I ' a It o -
II I It ll D u -
'" i' m. ([8!) n n v n owl?
, - - -
mum Bilt Bil, Bih
I “NIH:
a Whatunin
WM 80.01'” .
(mp m n D II urcm.
"f-l',
le uoeiciumm
= II - IIBHT JUITIFIED)
TL/H/5688-16
FIGURE 16. Input Connectlons and Controls for DAtM000-t002 Right Jutttlfled Data Option
DAC1000/ 1001 / 1 002 (24-Pln Parts)
M7 " Dis (MSII rm
L, t , tl n n
\ D a II n ---
n o i o t -
l-IIT Y tt mrur tl D n -
um nus l t 0 men n o o _
I ti 0 2 a man u - to
-lf " D n n tut u - £33139:
V an Ott (uh I: il , UM" tl _
" D "mu tl n u -
D LATCH o - n 0 -
- t - [mm m =1 o
"o-i. .
OUTPUTS mum n mans.
m n o It wantin' em
arm grWo-',',
iii/iii-'-
. (mum Loaac Is sum m
LF/u = I-un JUS‘IIFIED)
FIGURE 17. Input Connections and Controls for DAC1000-1002 Left Justified Data Option
DAC1006/1007/ 1008 (zo-Pin Parts for Left Justified Data)
" (Isl)
1U-BIT
RESIST”
0 CHINE!"
SMTBIIEB
:in mum;
rm 1 o a
N t o a
\ 4: tt wt il
0-." , ' D mp1" 0
umuu: t n man a
I , n u
I li u o
If 1. n il
”lo f " um i
.1,-F. D tll', a
t It urcn a
mm 3 am am
ii?r-'i-
135) m
arm ME! = 1.0
TPUTS Four»! , INPUTS.
= It, am
" o Is urcuso‘
TL/HMi688-tr
FIGURE 18. Input tttttttttttttttttttt and Controls for DAC1006/1007/ 1008 Left Justified Data
800 LOVG/l00l0VO/900lOVG/ZOOLOVCI/ lOOLOVO/OOOI-OVCI
DAC1000/DAC1001IDAC1002/DAC1006/DAC1007/DAC1008
6.2.1 Automatic Transfer
This makes use of a double byte (double precision) write. The first byte (8 bits) is strobed into the input latch and the second
byte causes a simultaneous strobe of the two remaining bits Into the input latch and also the transfer of the complete 10-bit word
from the input latch to the DAC register. This is shown in the following timing diagrams; the point in time where the analog output
is updated is also indicated on these diagrams.
DAC1000I 1000 1002 (24-Pln Parts)
a-\_.yi?"1c._/-
Lon In- t ??- LOAD m 2
sd /-rg um “:1 / um: m
m 11W ' urwzn
6.2.2 Transfer Using pP Write Stroke
DAC1006/ 1007/ 1008 (20-Pln Parte)
u\_/*\_f
mun" tt mnmum
.grurra I -Wllt) Mumm
M1 mam
-----2 OUTPUT
Itttstam
TuH/56g8-t8
‘SIGNIFIES CONTROL INPUTS WHICH ARE DRIVEN IN PARALLEL
The input latch is loaded with the first two write strobes. The XFER signal is provided by extemal logic, as shown below, to cause
the transfer to be accomplished on a third write strobe. This is shown in the following diagrams:
DAC1000/1 001 f 1 002 (24-Pln Parts)
n\__/*\__/Tmml
0 LATIN tut)
LEAD In. I LOAD m 2 UNITED REGISTER
mum / -urculyin / mcum!
13% 1) XFEI
------e, lee -..q.-..--
m um I
22 -----
m ttrt)
6.2.3 Transfer Using an External Strobe
DAC 1006/ 1 007/ 1008 (20-Ph Parts)
a1.-/"L-/,i,,',;'i,i,T,i,,-
LATER MC
uuo m 1 n L310 m , umm mum
- Um... "'iijdtr)r
m a Cir-
------i r_-__
htataitm N I
'tttEt-greet-Met-Nr-ttttit-tttee'.
'MrttftmEtNmtt_Eltt8Etrm0ttTti8M0ea"tt88le8tRu,
TL/H15688-19
This is similar to the previous operation except the XFER signal is not provided by the tsp. The timing diagram for this is:
DAC1000/ 100 1/1002 (24-Pln Parts)
'\__/**\_/*a
LOAD Iytt 1
uuo m t
- H ?--.
m / N 1e',","Tri'."l''jrilt, IN ,
m on “h o
unmn " t unit on
DAC t 006/1 007/ 1008 (20-Pln Parts)
a-)c_/")c._./'"""'"
Lm /m1 ?? mu m , ,2
Rt IL/sd),
mm m- t Uitttt m t
u R mu
3%, mm m:
----- - - - - -
hh 1/ /
y. - - - - -
TLYH/5MB-20
6.3 Interfacing to a 16-8" Data Bus
The interface to a 16-bit data bus is easily handled by connecting to 10 of the available bus lines. This allows a wiring selected
right justified or left justified data format. This is shown in the connection diagrams of Figures 79 and 20, where the use of DB6
to DB15 gives left justified data operation. Note that any part number can be used and the Bytei fByta2 control should be wired
JUSTIFIED
mm LEFT
DB) Mtg 111 No (HSII D II It tl "S!
N i' n u n tt -
\ _ o a ll ll -
. o o , th--
aging” l g g 'l'irlr g g "li? g . comm
wen nmmzn -
/ I n a n n svmcuzs
l t - D n n 0 -
F . n o o -
L . " a o n n -
Dlo nu I m. (M) m
'''lPtPd,t ' Ml, m “E" mm "
mr-.'.. oumrs mun} in mm.
a mu. um
Milo---- " t) us LAICNED.
(m. t,r,ge--sl
Bmp-a',
oJilf 'di-id''--',
FIGURE 19. Input Connections and Loglc for DACt000-1002 with 16-Blt Data Bus
LEFT l tut1im/ttlt1r/ttm8 IN-pm mus)
JUSTIFtEDI
us I m use us:
k " 'l gl I n n a a -
\ T n n u a -
' ' D D D tl -
ll n n u - u
tlMttt 41 tow a 0 man u - T
mm DAC cuunsur
IUTh BOS D wen tl tt nsslmn u - swans:
It II D ll -
n o u a -
o o ll n -
n u v ll n -
Mir , mo (LS!) ls!
I m f Tu u
H l ' mm mm
ii",'---
comm t ""‘Eim MIX: t,0
nus l outrun mm o Imus.
_ 4 'r-aC)-------------- WM: tt, am
1651mm I u It IS menu.
1'e,t.a..,.-u, (EQUIVALENT LOGIC sucwu
am mm- 2 t m ms PIN mum
TL/ H t 5888-21
FIGURE 20. Input Connections and Loglc for DAC1006/ 1007/1008 with IS-Blt Data Bus
BOOLOVG/LOOlOVO/90010VO/ZOOlOVGILOOIOVO/ODOIOVG
DAC1000/ DAC1001 I DAC1002/ DAC1006/ DAC1007/ DAC1008
Three operating modes are possihio: flow through, single buffered, or double buffered. The timing diagrams for these are shown
below:
6.3.1 Single Buffered
DAc1000/1001I1002 (24-Pln Parts)
Tn I 17iirf ANALOG
ll m1 \_/ N, urcuis mm m
htr 1afiiT=t unmrn/ I m mmm
LOAD INF!" U10" I
w" T0 twr “0151“
6.3.2 Double Buffered
DAC 1000/ 1001/ 1002 (24-Pln Parts)
"IIT DATA IS “101150
- N 'l--
"s um: mm mm
- ----e-, ---------
um um. t l
ttttttmira, ttlit/jr-h-r-hives,',"
W " m "
6.4 Stand Alone Operation
DAC1006/1 007/ 1008 (20-Pln Parts)
a N / xm mm mm
m IEBISTEI
ii mama \ f
M: n N. INPUT om us
l LAIBHED
Low m1 Lmu
DAC1006/ 1007/ 1 008 (20-Pln Parts)
a L.-...-;
mm um I: urcusu
's.. Lou: um um
- mm \ l
mu oumr "'sr m manta
um um t=t umm f it unusn
TL/H/5688-22
For applications for a DAG which are not under p.P c0ntrol (stand alone) there are two basic operating modes, single buffered
and double buffered. The timing diagrams for these are shown below:
6.4.1 Single Buttered
DAC1000/1001/1002 (24-P1n Parts)
wr)r_/irut, mm utcu
LOAD INN! INCH
6.4.2 Double Buffered
DAC1000/1001/1002 (24-Pln Parts)
F------
m -cycrrrt' mm urcu
LEAD III" MICK
',i,",T,r'"-T,ii.,iii,Cy.)1'/""C,,
= = 's
a m ' 'llll'g'l, sew
m 11W=1
DAC1006/1007/1008 (20-Pln Parts)
mu " an: nimm
"""m gnaw: l / /x
ANAL“, LITIHE! MT. "1 tut REGISYEI
WTNT ”INT am Ill“ IEIAIN VALID
IIPDMED ITIL I'HIS TWE)
DAC1006/1007/1008 (20-Pln Parts)'
UMtt II?!" uto
m “m , 0mm / ms.. um m
unmn - mum
a "m = u
_ mm mm um:
TL/H/5888-23
"For a connection diagram of this operating mode use Figure la tor the Logic end Figum 20 for the Data Input txmtttttttitmtt.
6.4.3 Flow Through
This operating mode causes the 10-bit input word to directly create the DAC output without any latching involved.
DAC1000] 1001/ 1002 (24-Pln Parts)
TmT--ihm2-0g--rFt!rFo
Byte 1/ Byte 2 == 1
7.0 MICROPROCESSOR INTERFACE
The logic functions of the DAC1000 family have been on'- The circuit will perform an automatic transfer of the 10 bits
ented towards an ease of interface with all popular pPs. The of output data from the CPU to the DAC register as outlined
following sections discuss in detail a few useful interface in Section 6.2.1, "Controlling Data Transfer for an a-Bit Data
schemes. Bus."
7.1 DAC1001/112to INSBOBOA Interface Since a double byte write is necessary to control the DAC
with the INS8080A, a possible instruction to achieve this is a
PUSH of a register pair onto a "stack" in memory. The 16-
bit register pair word will contain the 10 bits of the eventual
DAG input data in the proper sequence to conform to both
Figure 21 illustrates the simplicity of interfacing the
DAC1000 to an INS8080A based microprocessor system.
DATA BUS
Imam + 111v 1 Una; mmn yum
6ND " XFEH WM
ADDRESS nus
comm nus
TLO05688-24
NOTE: DOUBLE BYTE STORES CAN BE USED.
aa. THE INSTRUCTION SHLD F001 STORES THE L
REG INTO Bt AND THE H REG INTO B2 AND
TRANSFERS THE RESULT TO THE DAC REGISTER.
THE OPERAND OF THE SHLD INSTRUCTION MUST
BE AN ODD ADDRESS FOR PROPER TRANSFER.
FIGURE 21. Inttrrtattlrtg tho DAC1000 to the INSBOBOA CPU Group
800l-OVGILOOlOVCl/9OOIOVO/ZOOlOVGILOOLOVG/OOOI-OVG
DAC1000/DAC1001lDAC1002/DAC1006/DAC1007/DAC1008
the requirements of the DAC (with regard to right or left
justified data) and the implementation of the PUSH instruc-
tion which will output the higher order byte of the register
pair (i.e., register B of the BC pair) first. The DAC will actual-
ly appear as a two-byte “stack" in memory to the CPU. The
auto-decrementing of the stack pointer during a PUSH al..
lows using address bit 0 of the stack pointer as the Byte1/
Byte? and YFER strobes if bit 0 of the stack pointer address
--1, (SP-I), is a "1" as presented to the DAC. Additional
address decoding by the DM8131 will generate a unique
DAC chip select (CS) and synchronize this cs to the two
memory write strobes of the PUSH instruction.
To reset the stack pointer so new data may be output to the
same DAC, a POP instruction followed by instructions to
insure that proper data is in the DAC data register pair be..
fore it is "PUSHED" to the DAC should be executed. as the
POP instruction will arbitrarily alter the contents of a register
Another double byte write instruction is Store H and L Direct
(SHLD), where the HL register pair would temporarily con-
tain the DAC data and the two sequential addresses for the
DAC are specified by the instruction op code. The auto in-
crementing of the DAC address by the SHLD instruction
permits the same simple scheme of using address bit 0 to
generate the byte number and transfer Strobes.
7.2 DACtOOO to MC6820/1 PIA Interface
In Figure 22 the DAC1000 is interfaced to an M6800 system
through an MC6820/ 1 Peripheral Interface Adapter (PIA). In
this case the CS pin of the DAC is grounded since the PIA is
already mapped in the 6800 system memory space and no
decoding is necessary. Furthermore, by using both Ports A
and B of the PIA the 10-bit data transfer, assumed right
justified again in two 8-bit bytes, is greatly simplified. The
HIGH byte is loaded into Output Register A (ORA) of the
PIA, and the LOW byte is loaded into ORB. The 10-bit data '
transfer to the DAC and the corresponding analog output
change occur simultaneously upon CB2 going LOW under
program control. The 10-bit data word in the DAG register
will be latched (and hence VOUT will be fixed) when CB2 is
brought back HIGH.
It both output ports of the PIA are not available, it is possible
to interface the DAC1000 through a single port without
much effort. However, additional logic at the CB2(or CA2)
lines or access to some of the 6800 system control lines will
be required.
7.3 Noise Considerations
A typical digitaI/microprocessor bus environment is a tre-
mendous potential source of high frequency noise which
can be coupled to sensitive analog circuitry. The fast edges
of the data and address bus signals generate frequency
components of 10's of megahertz and can cause noise
spikes to appear at the DAC output. These noise spikes
occur when the data bus changes state or when data is
transferred between the latches of the device.
In low frequency or DC applications, low pass fiitoring can
reduce these noise spikes. This is accomplished by over-
compensating the DAC output amplifier by increasing the
value of the feedback capacitor (Cc in Figure a).
In applications requiring a fast transient response from the
DAC and op amp, filtering may not be feasible. Adding a
latch, DM74LS374, as shown in Figure 23 isolates the de-
vice from the data bus, thus eliminating noise spikes that
occur every time the data bus changes state. Another meth-
od for eliminating noise spikes is to add a sample and hold
after the DAC op amp. This also has the advantage of elimi-
nating noise spikes when changing digital codes.
FIGURE 22. DAC1000 to MC6820/1 PIA Interface
DMIIIDII
3113? LJ/TJEYFEE
TL/H/5688-25
f mun: l
i, s I a nun“
cm mus!" cr.1s
at: i In: nu
u u I I t I in let
um m " -
Vast oAcinos/twmnon mm "AUN
am" --o
mm W0 WTNT
a n in: me m " t
a a a " =
"Li's: m3:
"m. " NOTE: DATA HOLD TIME REDUCED TO THAT OF DM74L8374 Irc10 ns)
mun In L-c) yr-----------
(mm lm1
HM M "TE tl
FIGURE 23. Isolating Data Bus from DAC Circuitry to Ellmlnate Dlgltal Nolse Coupling
IS! [SB
151t o-
MlERO-BM:
DAE1MSERIES
1tREFitt
FIGURE 24. Dlgltally Controlled Amplitier/Attenuator
7.4 Dlgltally Controlled Amplltler/Attenuator
An unusual application of the DAC, Figure 24, applies the
input voltage via the on-chip feedback resistor. The lower
op amp automatically adjusts the VREF IN voltage such that
Iour, is equal to the input current MN/Fttg). The magnitude
of this VREF IN voltage depends on the digital word which is
in the DAC register. |OUT2 then depends upon both the
magnitude of Vm and the digital word. The second op amp
converts 'OUTZ to a voltage. VOUT: which is given by:
1023-N
VOUT=VIN(T)’ where 0 < NS 1023.
TLlH/5688-26
Note that N = o (or a digital code of all zeros) is not allowed
or this will cause the output amplifier to saturate at either
iVMAx. depending on the sign of Vm.
To provide a digitally controlled divider, the output op amp
can be eliminated. Ground the IOUT2 pin ot the DAC and
Van is now taken from the lower op amp (which also drives
the VREF input of the DAC). The expression for VOUT is now
given by
VoUT= _.lf1?f where M = Digital input Sexpressed as a
M fractional binary number' .
0300lOVG/LOOI-OVG/SOOlOVG/ZOOlOVG/ lOOlOVOIOOOLOVG
DAC1000/DAC1001/DAC1002/DAC1006/DAC1007/DAC1008
LF13333 TI
- V55; SING: X -
OUADMNT
DECODE
Um: case = , S3
TL/H/5688-27
FIGURE 25. Digital to Synchro Converter
Ordering Information
1. All Logic Features - 24-pin package.
Temperature Range
Accuracy
-40°c to + 85'C -55''C to + 125°C 0" to + 70°C
005% (10-bit) DAC1000LCJ DAC1000LJ DAC 1000LCN
0.10% (9-bit) DAC1001LCN
0.20% (8-bit) DAC1002LCJ DAC1002LJ DAC1002LCN
Package Outline J24A J24A N24A
2. For Left Justified Data - 20-pin package.
Temperature Range
Accuracy
--4trc to + 85''tt - 55°C to +125°c tr' to + 7tt'C
0.05% (1 O-bit) DAC1 006LCJ DAC1006LJ DAC1006LCN
0.10% (9-bit) DAC1007LCN
0.20% (8-bit) DAC1008LCJ DAC1008LJ DAC1008LCN
Package Outline J20A J20A N20A
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
DAC1002LJ - product/dac1002Ij?HQS=T|-nu|l-nu|l-dscatalog-df-pf—null-wwe
DAC1008LJ - product/dac1008lj?HQS=T|-nu|I-nu|I-dscatalog-df—pf—null-wwe
DAC1008LCJ - product/dac1008lcj?HQS=T|—null-nulI-dscatalog-df-pf-nuII-wwe
DAC1006LJ - product/dac1006|j?HQS=T|—nu|l-nu|I-dscatalog-df—pf-null-wwe
DAC1006LCJ - product/dac1006|cj?HQS=TI-null-nulI-dscataIog-df-pf-null-wwe
DAC1000LCJ - product/dac1000|cj?HQS=T|—nu||-nu|I-dscatalog-df-pf-nuII-wwe
DAC1000LCN - product/dac1000lcn?HQS=TI-null-nu|I-dscataIog-df-pf-null-wwe
DAC1000LJ - product/dac1000|j?HQS=T|—nu|l-nu|I-dscatalog-df—pf-null-wwe
DAC1001LCN - product/dac1001|cn?HQS=TI-nulI-nu|I-dscataIog-df-pf-null-wwe
DAC1002LCJ - product/dac1002lcj?HQS=T|—nu||-nu|I-dscatalog-df-pf-nuII-wwe
DAC1002LCN - product/dac1002lcn?HQS=TI-null-nu|I-dscatalog-df—pf-null-wwe
