DAC0832LCJ ,8-Bit P Compatible/ Double-Buffered D to A ConvertersDAC0830/DAC0832 8-Bit μP Compatible, Double-Buffered D to A ConvertersMay 1999DAC0830/DAC08328-Bit ..
DAC0832LCM ,8-Bit P Compatible/ Double-Buffered D to A ConvertersFeaturesn Double-buffered, single-buffered or flow-through digitalThe DAC0830 is an advanced CMOS/S ..
DAC0832LCM ,8-Bit P Compatible/ Double-Buffered D to A ConvertersFeaturesn Double-buffered, single-buffered or flow-through digitalThe DAC0830 is an advanced CMOS/S ..
DAC0832LCN ,8-bit Microprocessor Compatible, Double-Buffered D/A ConverterFeaturesn Double-buffered, single-buffered or flow-through digitalThe DAC0830 is an advanced CMOS/S ..
DAC0832LCV ,8-bit Microprocessor Compatible, Double-Buffered D/A ConverterFeaturesn Double-buffered, single-buffered or flow-through digitalThe DAC0830 is an advanced CMOS/S ..
DAC0832LCWM ,8-bit Microprocessor Compatible, Double-Buffered D/A ConverterFeaturesn Double-buffered, single-buffered or flow-through digitalThe DAC0830 is an advanced CMOS/S ..
DL207 , SILICON RECTIFIER DIODES
DL207 , SILICON RECTIFIER DIODES
DL207 , SILICON RECTIFIER DIODES
DL-3039-011 ,Index Guided AlGalnP Laser DiodeOrdering number: EN5865Red Laser DiodeDL-3039-011Index Guided AlGalnP Laser DiodeOverview Package D ..
DL-3416 , 4-Character 16 Segment Plus Decimal Alphanumeric Intelligent Display®
DL4001 , SURFACE MOUNT RECTIFIERS (REVERSE VOLTAGE: 50 - 1000 V CURRENT: 1.0 A)
DAC0831LCN
17 V, 8-bit uP compatible, double-buffered D/A converter
DACOBSO/DA00831/DACO832
[ National
Semiconductor
DAC0830f0AC0831/DAC0832 8-Bit MP
Compatible, Double-Buffered D to A Converters
General Description
The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying
DAC designed to interface directly with the 8080, 8048,
8085, 2800, and other popular microprocessors. A deposit-
ed silicon-chromium R-2R resistor ladder network divides
the reference current and provides the circuit with excellent
temperature tracking characteristics (0.05% of Full Scale
Range maximum linearity error over temperature). The cir-
cuit uses CMOS current switches and control logic to
achieve low power consumption and low output leakage
current errors. Special circuitry provides TTL logic input volt-
age level compatibility.
Double buffering allows these DACs to output a voltage cor-
responding to one digital word while holding the next digital
word. This permits the simultaneous updating of any num-
ber of DACs.
The DACOSSO series are the 8-bit members of a family of
microprocessor-compatible DACs (MIGR0-DACrM). For ap-
plications demanding higher resolution, the DAC1000 series
(1 O-bits) and the DAC1208 and DAC1230 (12-bits) are avail-
able alternatives.
Features
I: Double-buttered, single-buffered or flow-tttrough digital
data inputs
n Easy interchange and pin-compatible with
DAC1230 series
" Direct interface to all popular microprocessors
II Linearity specified with zero and tuil scale adjust only---
NOT BEST STRAIGHT LINE FIT.
u Works with i10V reference-tuil 4-quadrant
multiplication
I: Can be used in the voltage switching mode
ll Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
" Operates "STAND ALONE" (without pP) if desired
gt Available in 20-pin smali-outline or molded chip carrier
package
1 2-bit
Key Specifications
" Current settling time 1 ps
a Resolution 8 bits
a Linearity 8, 9, or 10 bits
(guaranteed over temp.)
n Gain Tempoo 0.0002% FS/''C
I: Low power dissipation 20 mW
a Single power supply 5 to 15 VDC
Typical Appllcatlon
“ng "’5 'Allows easy upgrade to 12-bit DAC1230,
See application hints
III "ttt trt"itt)
a " " " 1 1 " ' ttttttt
, mmwmumz " -qtogt
' a a 10 +
IMO Ills Nun - -
TuH/5608-1
Connection Diagrams [Top Views)
DuaI-In-Llne and Molded Chip Carrier Package
Smail-Outllne Packages WITH! tIts as on.
F: _ 10 n _ m tThis is necessary for the i: 17 " IS "
F, __i 2 ., k..- mmmm" 12-bit DAC1230 series to " (MI/ 81111)? " I -u,(uss)
sun - 3 u - EL permit interchanging from Van ‘lotm
Ill, - a " - ‘m an 8-bit to a 12-bit DAC ls "mm
Ott - ' '6 - th with No " board changes Wit, -9",
m - I Is - ths ao '-Rib
Me Mn - t " - m. and no software changes. I
Irm -.1 I " - uh "am See appiications section.
a. - ' u - Inn" h Iltt M, ths Van
III - IO IT - 1W. TLfH/5608-22
TL/H/5608-m
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace spetMed devlces are required,
please contact the National Semiconductor Sales
0fflttefDltttrlbutortt for availability and speclficatlons.
Supply Voltage (Vcc) 17 VDC
Voltage at Any Digital Input VCC to GND
Voltage at VREF Input f, 25V
Storage Temperature Range
Package Dissipation
- 65'C to + 150°C
at TA = 25°C (Note 3) 500 mW
DC Voltage Applied to
ioun or Iowa (Note 4) - 100 mV to vcc
ESD Susceptability (Note 14) 800V
Lead Temperature (soldering, 10 sec.)
Dual-ln-Line Package (plastic)
Dual-ln-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
Operating Conditions
Temperature Range
Part numbers with 'LCN' suffix
Part numbers with 'LCWW suffix
Part numbers with 'LCV' suffix
Part numbers with 'LCJ' suffix
Part numbers with 'LJ' suffix
Voltage at Any Digital Input
300''C
TMINSTASTMAX
0°C to + 70''C
0°C to + 70"C
0"C to + 70°C
--4trc to + 85''C
-55"C to + 125°C
Vcc to GND
Electrical Characteristics VREF=10.000 VDC unless otherwise noted. Boldface limits apply over tempera-
ture, Tam: STA S TMAX- For all other limits TA = 25'C.
= Vcc = 5 VDC i5%
Vcc 4.75 VDC Mce = 12 ch :5%
See Vcc = 15.75 VDC to " v + 5% Limit
Parameter Conditions Dc -
Note Unlts
Tested .
Typ Llmit Design Limit
(Note 12) (Note 5) (Note 6)
CONVERTER CHARACTERISTICS
Resolution 8 B tt bits
Linearity Error Max Zero and full scale adjusted 4, 8
-10VscVmrs +10V
DAC0830LJ & LCJ 0.05 0.05 % FSR
DAC0832LJ 8 LCJ 0.2 0.2 % FSR
DAC0830LCN, LCWM & LCV 0.05 0.05 % FSR
DAC0ty31LCN 0.1 0.1 % FSR
DAC0832LCN, LCWM 8. LCV 0.2 0.2 % FSH
Differential Nonlinearity Zero and full scale adjusted 4, 8
Max -10VegVREFsc+10V
DAOOBBOLJ & LCJ 0.1 0.1 oh, FSR
DAC0832LJ & LCJ 0.4 0.4 % FSR
DAC0830LCN, LCWM & LCV 0.1 0.1 % FSR
DA00831LCN 0.2 0.2 % FSR
DAC0832LGN, LCWM & LCV 0.4 0.4 % FSR
Monotonicity --10V I VREF Ll & LCJ 4 tt tt bits
s: +10V LCN, LCWM & LCV 8 8 bits
Gain Error Max Using Internal Rm 7 o
-10VsrVREFsr+-10V i0.2 cel +1 /oFS
Gain Error Tempco Max Using internal Rib 0.0002 0.0006 FS/;°C
Power Supply Rejection All digital inputs latched high
Vcc = 14.5V to 15.5V 0.0002 0.0025 %
11.5V to 12.5V 0.0006 FSR/V
4.5V to 5.5V 0.013 0.015
Reference Input Max 1 s 2O 20 kn
Min 1 tt 1 tt 1 o k0.
Output Feedthrough Error VREF = 20 Vp-p, f--- 100 kHz 3 mV -
All data inputs latched low p p
ZSSOOVG/ lSSOOVG/OSBOOVG
DACOB30IDACOB31/DACOB32
Electrical Characteristics VREF= 10.000 Voc unless otherwise noted. Boldface limits apply over tempora-
ture, TMINSTA scTwut. For all other limits a-- 25''C, (Continued)
Vcc = SVDtt i596
','/irC,1?,ilt,e, vcc 7.'l.% " vac 15%
See ce I DC to " ch 16% len
Parameter Conditions
Note Units
Tested
Typ lelt Design lelt
(Note 12) (Note lil (Note 6)
CONVERTER CHARACTERISTICS (Continued)
Output Leakage loun All data inputs LJ 8. LCJ 10 100 100 nA
Current Max latched low LCN, LCWM 8. LCV 50 1 oo
Iowa All data inputs Ll & Ltll 1 00 100 nA
latched high LCN, LCWM & LCV 50 1 00
Output IOUT1 All data inputs 45 F
Capacitance knmt latched low 1 15 p
Iotm All data inputs 130 F
IOUTZ latched high so p
DIGITAL AND DC CHARACTERISTICS
Digital Input Max Logic Low Ll 4.75V 0.6
Voltages Ll 15.75V 0.8
LCJ 4.75V 0.1 vac
LCJ 15.75V 0.8
LCN, LCWM, LCV 0.95 0.8
Min Logic High LJ & LCJ 2.0 2.0 V
LCN, LCWM, ch 1.9 2.0 DC
Digital Input Max Digital inputs
Currents Ll & LCJ -50 --20tt --200 p.A
LCN, LCWM, LCV - 160 -200 PA
Digital inputs > 2.0V
Ll & LCJ tht + " + " pA
LCN, LCWM. LCV +8 + "
Supply Current Max LJ & LCJ 1.2 3.5 3.5 m A
Drain LCN, LCWM, LCV 1.7 2.0
Electrical Characteristics VREF == 10.000 VDc unless otherwise noted. Boldface llmlts apply over tempera-
ture, TMIN S TA STMAX. For all other limits TA = 25°C. (Continued)
= 1ftxt----t2Vntg*5% = Vcc=5VDc
Vee 15.75 Vpc to " VDC 15% Vet; 4.75 Voc d:5%
s tr l p t c am Sett Limit
ym o arame er on one Note T Tested Design T Tested Design Units
odd l 2) Llmlt Limit (N05; 2) Limit lelt
(Note S) (Note 6) (Note 5) (Note 6)
AC CHARACTERISTICS
ts Chrrent Setting " = 0V, VIH = SV 1.0 1.0 ps
tw Write and XFEFt Ve-- OV, VIH = 5V 11 100 250 375 600
Pulse Width Min 9 320 320 900 900
tos Data Setup Time " = ov, " = 5V 9 100 250 375 600
Min a 20 a 20 900 soo
tDH Data Hold Time Vc-" 0V, VIH --.= 5V 9 30 50 ns
Min 30 Stt
tcs Control Setup Time Iht. = ov, " = 5V 9 1 10 250 600 900
Min 320 320 1 100 1 100
tCH Centrol Hold Time " = ov, VIH = 5V 9 0 0 , O 0 o
Min o o
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND. unless otherwise specified.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX. tua, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperatue is PD = (TJMAX - TA)/0JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, Twax --. 125'0 (ptestic) or 15tt'C (ceramic). and the typical iunction-to-embient thermal resistance at the J package when board mounted is 80'C/W. For
the N package, this number increases to 100'C/W and tor the V package this number is 120'C/W.
Note 4: For current switching applications. both Icon and Ioure must go to ground or the “Vitus! Ground“ of an operational amp6fier. The linearity error is
degraded by approximately vos + VREF. For example, if VREF = 10V then a 1 mV offset, vos, on low” or tours, will introduce an additional 0.01% linearity error.
Note 5: Tested limits are guaranteed to Nationars AOQL (Average Outgoing Quality Level).
Note tk Guarantssxi, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note r.. Guaranteed at VREF= * 10 VDC and VREF-- 11 VDO
Note Ir: The unit "FSR" stands tor "Full Scale Range." "Linearity Error" and "Power Supply Reiection" specs are based on this unit to eiiminate dependence on a
particular VREF value and to indicate the true pertomtance of the part. The ''Unearity Error" specifcation of the DA00830 is "th05% of FSR (MAX)". This
guarantees that after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within
0.05%XVHEF of a straight line which passes through zero and full scale.
Note 9: Boidtace tested Emits apply to the Ld and LCJ suffix parts only.
Note to.. A 100M leakage current with Rm=20k and VREF=1OV corresponds to a zero error of000x 10‘9X20X103)>< 100110 which is 0.02% of FS.
Nate " The entire write pulse must occur within the valid data interval for the specified tw, ttss, ttm, and ts to appty.
Note 12: Typical: are at 25''C and represent most likely parametric norm.
Note 13: Human body model, 100 pF discharged though a 1.5 m resistor.
ZSSOOVG/ lSSOOVG/OEBOOVO
DACOB30/DAC0831IDACOB32
Switching Waveform
ILE. 7 5096
tett SON
DATA IITS
rt; --v
ioun lwn l
Definition of Package Pinouts
Qntrol Signals (All control signals level actuated)
Chip Select (active low). The Cg in combina-
tion with ILE will enable WAT
Input Latch Enable (active high). The ILE in
combination with ug enables 1TMT
Write t. The active low iiiltTi is used to load the
digital input data bits (DI) into the input latch.
The data in the input latch is latched when wr,
is high. To update the input latch-EA and R/AT
must be low while ILE is high.
Write 2 (active low). This signal, in combination
with X'FER. causes the 8-bit data which is avail-
able in the input latch to transfer to the DAC
register.
Transfer control slgnal (active tow). The
XFER will enable w-Ra.
Other Pln Functions
DIo-Dl7:
Dlgltal Inputs. Dlo is the least significant bit
(LSB) and DI? is the most significant bit (MSB).
DAC Current Output 1. loun is a maximum
for a digital code of alt 1's in the DAC register,
and is zero for all 0's in DAC register.
DAC Current Output 2. IOUT2 is a constant
minus loun, or lOUT1+IOUT2=constant (l full
scale for a fixed reference voltage).
Feedback ResistOr. The feedback resistor is
provided on the IC chip for use as the shunt
SETTLE!) TO
I the"
TL/H/5608-2
feedback resistor tor the external op amp which is
used to provide an output voltage for the DAC.
This on-chip resistor should always be used (not
an external resistor) since it matches the resistors
which are used in the on-chip Ft-2R ladder and
tracks these resistors over temperature.
Reference Voltage Input. This input connects an
external precision voltage source to the internal R-
2R ladder. VHEF can be selected over the range of
+ 10 to -10V. This is also the analog voltage in-
put for a 4-quadrant multiplying DAC application.
Digital Supply Voltage. This is the power supply
pin for the part. Voc can be from + 5 to + 15VDC-
Operation is optimum for +15VDC.
The pin 10 voltage must be at the same ground
potential as Iour1 and '0UT2 for current switching
applications. Any difference of potential Nos pin
10) will result in a linearity change of
vos pin 10
For example, if VREF = 10V and pin 10 is 9mV
offset from Iourt and IOUT2 the linearity change
will be 0.03%.
Pin 3 can be offset k100mV with no linearity
change, but the logic input threshold will shift.
Linearity Error
h LS! [MUN
ANALOG OUTPUT
AN ALDO OUTPUT
DIGITAL INPUT
ttl End point test after
zero and ts ad].
Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DACOBSO
has 28 or 256 steps and therefore has 8-bit resolution.
Linearity Error: Linearity Error is the maximum deviation
from a straight line passing through the endpoints of the
DAG transfer characteristic. It is measured after adjusting
for zero and fulI-scaie. Linearity error is a parameter intrinsic
to the device and cannot be extemaliy adjusted.
National's linearity "end point test" (a) and the "best
straight line" test (b.c) used by other suppliers are illustrated
above. The "end point test" greatly simplifies the adjust-
ment procedure by eliminating the need for multiple itera-
tions of checking the linearity and then adjusting full scale
until the linearity is met. The "end point test" guarantees
that linearity is met after a single full scale adjust. (One ad-
justment vs. multiple iterations of the adjustment.) The "end
point test" uses a standard zero and ES. adjustment proce-
dure and is a much more stringent test for DAC linearity.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
fuiI-scaie output.
IDEAL RESPONSE
DIBH’IL INPUT
b) Beat straight line
th LS! EIIM ""
1 LS! [IRON
ANALOG OUTPUT
DIGITIL INPUT
TLIH/seos-a
0) Shining ts ad]. to pass
best stralght line teat
Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within inLSB of
the final output value. Full-scale strttling time requires a zero
to fuiI-scale or tuII-scale to zero output change.
Full-Seaie Error: Full scale error is a measure of the output
error between an ideal DAG and the actual device output.
Ideally, for the DACOBSO series, tulI-scaie is VREF TILSB.
For VREF=1OV and unipolar operation, VFULL-SCALE=
1th0000V-39mV= 9.961 V. FulI-scaie error is adjustable to
Differential Nortllrtetsrttyt The difference between any two
consecutive codes in the transfer curve from the theoretical
1 LSB is differential nonlinearity.
"tttttttttttlet If the output of a DAG increases for increasing
digital input code, then the DAC is monotonic. An 8-bit DAC
which is monotonic to 8 bits simply means that increasing
digital input codes will produce an increasing analog output.
r'"''""" ___________ .___.1
(union "I u o h ll
'l1tp7pr.C, .. (,' .. -tr"'"
tet-',-','!--- tt a D a r---i-"-ouo,
1'uo-'-H--o am a V 0 Hit 0 oh,'l'm, l
m c " n NNT a MC tl m " [m
a si neutrino REGISTER comma! ,
tsto-u.--, n o n 0 u,,
mo-U--., o o n o i n...
I mm: mm
" 'T'', DITA AT 0 i3 MIMI.
ir . I
t-ot'ro
p-u-o ht
'r', u outrun mun n mms; 'l''---
TL/H/BGOB-l
FIGURE 1. DAcosao Functional Diagram
ZBBOOVG/ l- SBOGVGIOEBOOVG
DAC0830/DAC0831/DA00832
Typical Performance Characteristics
Digital Input Threshold
vs. Itec
Digital Input Threshold
t ' vs. Temperature
Gain and Linearity Error
Variation vs. Temperature
_ 2.0 g = -55 -oiEhlilWEMtm
e. 2 7 0.05 ... man
9 1.5 a = ' -
2' ES 1. " c 5 0.025
a 12 m - o E
E E n-125 c . n
5 M S ts 4.025
E E E. 41.05
-0.trrs =15
45-35-15 5 " " as 115105125 ' ttl 15 -55-M-N ' " as " " 105125
1.. Anatsut Izmsmuns 1°C) Ax, SUPPLY #0Ltlrt1t [Vt n. mutant TEMPERATURE CC)
Gain and Linearity Error
Variation vs. Supply Voltage Write Pulse Width Data Hold Ttme
+0.02: son
autumn" emu / c
Mon - / s'. 250
7 'sl"''-";:,' 'k'
I -0.825 mm E M" V''' " 2 200
a ". 300 ,/ / s
Ir, -tht15 tD ,--'" " Vcc-5V = vcc=sv. m. ll,
z F. ,,.-'' “W" r, 150 Vm-av 1111-31!
H, 4.075 a too " g l vccssv.
g f, " g 100 West“. Itll, tMI
r", -tMiltl , :ccrgav // k' vm-sv _5V
s 100 "ite.'.,--" w-"''''" t
4.125 F- -- _ 50
r-' vcc-uv. must: a
m; =1“. vm-sv u " -
ll 5 IL! 15
llti:. SUPPLY VOLTAGE Natl
DAC0830 Series Application Hints
These DAC's are the industry's first microprocessor com-
patible, doubie-buffered 8-bit multiplying D to A converters.
Double-buffering allows the utmost application flexibility
from a digital control point of view. This 20-pin device is also
pin for pin compatible (with one exception) with the
DAC1230, a 12-bit MICRO-DAC. In the event that a sys-
tem's analog output resolution and accuracy must be up-
graded, substituting the DACt 230 can be easily accom-
plished. By tying address bit Ao to the ILE pin, a two-byte pp
write instruction (double precision) which automatically in-
crements the address for the second byte write (starting
with Ao--- "1") can be used. This allows either an 8-bit or the
12-bit part to be used with no hardware or software chang-
es. For the simplest 8-bit application. this pin should be tied
to Vcc (also see other uses in section 1.1).
Analog signal control versatility is provided by a precision l
2R ladder network which allows full 4-quadrant multiplica-
tion of a wide range bipolar reference voltage by an applied
digital word.
1.0 DIGITAL CONSIDERATIONS
A most unique characteristic of these DAC's is that the 8-bit
digital input byte is double-buftered. This means that the
data must transfer through two independently controlled tr.
bit latching registers before being applied to the R-2R lad-
der network to change the analog output. The addition of a
second register allows two useful control features. First, any
DAC in a system can simultaneously hold the current DAC
data in one register (DAC register) and the next data word in
the second register (input register) to allow fast updating of
the DAC output on demand. Second, and probably more
important, double-buffering allows any number of DAC's in a
-55-35-15 ' N " 65 051115.125
Th. AMBIENT TEM'ERMURE (NI)
-55-35-15 5 " " " 85105125
h. AMBIENT TEMPERATURE I'C)
TUFO 5608-5
system to be updated to their new analog output levels
simultaneously via a common strobe signal.
The timing requirements and logic level convention of the
register control signals have been designed to minimize or
eliminate external interfacing logic when applied to most
popular microprocessors and development systems. It is
easy to think of these converters as 8-bit "writer-only" mem-
ory locations that provide an analog output quantity. All in-
puts to these DAC's meet TTL voltage level specs and can
also be driven directly with high voltage CMOS logic in non-
microprocessor based systems. To prevent damage to the
chip from static discharge, all unused digital inputs should
be tied to Vcc or ground. If any of the digital inputs are
inadvertently left floating, the DAC interprets the pin as a
logic "I ".
1.1 Double-Buftered Operation
Updating the analog output of these DAC's in a double-butt-
ered manner is basically a two step or double write opera-
tion. In a microprocessor system two unique system ad-
dresses must be decoded, one for the input latch controlled
by the c-s pin and a second for the DAC latch which is
controlled by the XFER line. If more than one DAC is being
driven, Figure 2, the ES line of each DAC would typically be
decoded individually, but all of the converters could share a
common XFER address to allow simultaneous updating of
any number of DAC's. The timing for this operation is
shown, Figure a
it is important to note that the analog outputs that will
change after a simultaneous transfer are those from the
DAC's whose input register had been modified prior to the
XFEFt command.
DACOB30 Series Application Hints (Continued)
ANALOG
00TNT ,
_ILE Wi
xrsn iirii
ADDRESS
amaanma
ANALOG
OUTPUT t
ANALOG
" wr, ounur n
srsmf M W 'iWi
SYSIEN 7tt
"TIE TO LOGIC 1 IF NOT NEEDED (SEE SEC. 1.1).
FIGURE 2. Controlling Mutlple DACs
iMif ' Witt WU
INPUI LATCH ANALOG OUTPUT ,V nu; REGISTER LITCHED
UPDAIED UPDM’ED
iLE=LOGIC "I'' "c,._.._y/-""-
TLtH/5608-6
FIGURE 3
The ILE pin is an active high chip seIect which can be de- one controlling the DAC's to take over control of the data
coded from the address bus as a qualifier for the normal t% bus and control lines. If this second system were to use the
signal generated during a write operation. This can be used same addresses as those decoded tor DAC control (but for
to provide a higher degree of decoding unique control sig- a different purpose) the ILE function would prevent the
nets tor a particular DAC, and thereby create a more efti- DAC's from being erroneously altered.
Ciem addressing scheme. in a "Stand-Alone" system the control signals are generat-
Another useful application of the ILE pin of each DAC in a ed by discrete logic. In this case double-buffering can be
multiple DAC system is to tie these inputs together and use controlled by simply taking cg and WEA to a Iogie "o", ILE
this as a control line that can effectively "freeze" the out- to a logic "l" and pulling ir/AT low to load data to the input
puts of all the DAC's at their present value. Pulling this line latch. Pulling WAT, low will then update the analog output. A
low latches the input register and prevents new data from logic "r' on either of these lines will prevent the changing
being written to the DAC. This can be particulariy useful in of the analog output.
multiprocessing systems to allow a processor other than the
ZS800VG/ lEBOOVG/OEBOOVG
DACOB30/DACOB31/DACOB32
DAC0830 Series Application Hints (Continued)
ANALOG om
OUTPUT urumn utcuso
TL/Hl5605-7
IE-- LOGIC "1"; W and RTEA GROUNDED
FIGURE 4
1.2 Single-Buffered Operation
In a microprocessor controlled system where maximum be met or erroneous data can be latched. This hold time is
data throughput to the DAC is of primary concern, or when defined as the length of time data must be held valid on the
only one DAC of several needs to be updated at a time, a digital inputs after a qualified (via ts) WIA strobe makes a
single-butfered configuration can be used. One ot the two low to high transition to latch the applied data.
internal r.Nstere allows the data to flow through and the If the controlling device or system does not inherently meet
other register will serve as the data latch. these timing specs the DAC can be treated as a slow mem-
Digital signal feedthrough (see Section 1.5) is minimized if cry or peripheral and utilize a technique to extend the write
the input register is used as the data latch. Timing for this strobe. A simple extension of the write time, by adding a
mode is shown in Figure 4. wait state, can simultaneously hold the write stro_bg active
Single-buffering in a "stand-alone" system is achieved by and data 1alid. on tht, bus to satisfy the minimum WR .pulst
strobing WrTf low to update the DAC with ' Ctrl?? and width. If this does not provide a suffityent data hold time at
Wit-tT grounded and ILE tied high. the end of the write cycle, a negative edge triggered one-
shot can be included between the system write strobe and
1.3 Flow-Through Operation the WA pin of the DAC. This is illustrated in Figure 5 for an
Though primarily designed to provide microprocessor inter- exemplary system which provides a 250ns W strobe time
face compatibility, the MlCRO-DAC's can easily be config- with a data hold time of less than 10ns.
ured to allow the analog output to continuously reflect the The proper data set-up time prior to the latching edge (LO to
state of an applied digital input. This is most useful in appii- HI transition) of the WA strobe, is insured it the WA pulse-
cations where tht? DAG is used in a continuous feedback width is within spec and the data is valid on the bus for the
control loop and is driven by a binary up-d0wn counter, or in duration of the DAC m strobe.
function generation circuits where a ROM is continuousiy
providing DAC data. 1.5 Digital Signal Feedthrough
Simply grounding a. WAi, WRE. and XF-ER and tying ILE When data is latched in the internal registers, but the digital
high allows both internal registers to follow the applied digi- inputs are changing state, a narrow spike of current may
tal inputs (fiow-through) and directly affect the DAC analog flow out of the current output terminals. This spike is caused
output. by the rapid switching of internal iogic gates that are re-
sponding to the input changes.
There are several recommendations to minimize this etfect.
When latching data in the DAC, always use the input regis-
1.4 Control Signal Timing
When interfacing these MICRO-DAC to any microprocessor,
there are two importanttime relationships that must be con- ter as the latch. Second, reducing the vcc supply for the
Litltrred to insure PTOPGI' operation. The first is the minimum DAC from + 15V to + 5V offers a factor of 5 improvement in
WB strobe pulse width which is specified as 900 ns for all the magnitude of the ftrtstithrough, but at the expense of
valid operating conditions of supply _voltage and 1rPiaitt Internal logic switching speed. Finally, increasing Co (Figure
temperature. but typically a pulse width o) only 180ns Is a) to a value consistent with the actual circuit bandwidth
adequate if Vcc=15VDc- A second consideration is that requirements can provide a substantial damping effect on
the guaranteed minimum data hold time of 50ns should any outputspikes.
DAC0830 Series Application Hints (Continued)
om nus
SYSTEM ans - A
wan: smuas - - snot mom Jk, 03%“?
'tl', X um nun y
wuess',i'td _ ---l F- SYSTEM am Hot!) mi: t< ions)
TR E ---- -
NORMAL . l i on: wan
-mifi STBDBE sure -
(25:: m) (mm
(00TNT 0F
onesmm
F 'st5 mom 'I
[35mm MO
-H om How TIME
(160 nsl
TLDO5608-8
FIGURE 5. Accommodating a High Speed System
2.0 ANALOG CONSIDERATIONS
The fundamental purpose of any D to A converter is to pro-
vide an accurate analog output quantity which is representa-
tive of the applied digital word. In the case of the DAC0830,
the output, Iotm, is a current directly proportional to the
product of the applied reference voltage and the digital input
word. For application versatility, a second output, Ioura, is
provided as a current directly proportional to the comple-
ment of the digital input. Basically:
= VREF X Digital input.
OUTI 15 m 256
I = VREF 255 - Digital Input
OUT2 15 m 256
where the digital input is the decimal (base 10) equivalent of
the applied B-bit binary word (0 to 255), VREF is the voltage
at pin 8 and 15 kn is the nominal value of the internal resist-
ance, R, of the R-2R ladder network (discussed in Section
Several factors external to the DAC itself must be consid-
ered to maintain analog accuracy and are covered in subse-
quent sections.
2.1 The Current Switching R-2R Ladder
The analog circuitry, Figure tr, consists of a silicon-chromi-
um (SiCr or Si-chrome) thin film R-2R ladder which is depos-
ited on the surface oxide of the monolithic chip. As a result,
there are no parasitic diode problems with the ladder (as
there may be with diffused resistors) so the reference volt-
age, VREF, can range --10V to +10V even if Vcc for the
device is SVDC.
The digital input code to the DAC simply controls the posi-
tion of the SPOT current switches and steers the available
ladder current to either lour1 or IOUT2 as determined by the
logic input level ("1" or "o'') respectively, as shown in
Figure 6. The MOS switches operate in the current mode
with a small voltage drop across them and can therefore
switch currents of either polarity. This is the basis tor the 4-
quadrant multiplying feature of this DAC.
2.2 Basic Unipolar Output Voltage
To maintain linearity of output current with changes in the
applied digital code, it is important that the voltages at both
of the current output pins be as near ground potential
(OVDC) as possible. With VHEF= +10V every millivolt ap-
pearing at either loun or lou-rg will cause a 0.01% linearity
error. In most applications this output current is converted to
a voltage by using an op amp as shown in Figure 7.
The inverting input of the op amp is a "virtual ground" creat-
ed by the feedback from its output through the internal 15
kn resistor, Rm. All ot the output current (determined by the
digital input and the reference voltage) will flow through Rm
to the output of the amplifier. Two-quadrant operation can
be obtained by reversing the polarity of VREF thus causing
Iour, to flow into the DAC and be sourced from the output
of the amplifier. The output voltage. in either case, is always
equal to Iour, anb and is the opposite polarity of the refer-
ence voltage.
The reference can be either a stable DC voltage source or
an AC signal anywhere in the range from -10V to + 10V.
The DAC can be thought of as a digitally controlled attenua-
tor: the output voltage is always less than or equal to the
applied reference voltage. The VREF terminal of the device
presents a nominal impedance of 15 kn to ground to exter-
nal circuitry.
Always use the internal be resistor to create an output volt-
age since this resistor matches (and tracks with tempera-
ture) the value of the resistors used to generate the output
current ilourd.
ZSSOOVGILSWOVG/OSSOOVG
DACOB30/ DACOB31 I DACOB32
DAC0830 Series Application Hints (Continued)
non. . . q .4-1n “m
' 0 ban
-42 ‘0012
FIGURE 8
n... (mmuut)
Hm laun " -
l ' V001 = -hrm X "mi
= Jim (DIGITAL mmm
- An musr
FIGURE , "c Tuwseoe-e
2.3 Op Amp Considerations
The op amp used in Figure 7 should have offset voltage
nuiiing capability (See Section 2.5).
The selected op amp should have as low a value of input
bias current as possible. The product of the bias current
times the feedback resistance creates an output voltage er-
ror which can be significant in low reference voltage appli-
cations. BI-FET op amps are highly recommended for use
with these DACs because of their very low input current
Transient response and settling time ot the op amp are im-
portant in fast data throughput applications. The largest sta-
bility problem is the feedback pole created by the feedback
resistance. Rm, and the output capacitance of the DAC.
This appears from the op amp output to the (-) input and
includes the stray capacitance at this node. Addition of a
lead capacitance. G: in Figure tr, greatiy reduces overshoot
and ringing at the output for a step change in DAC output
current.
Finally, the output voltage swing of the amplifier must be
greater than VREF to allow reaching the full scale output
voltage. Depending on the loading on the output of the am-
plifier and the available op amp suppty voltages (onty l 12
volts in many development systems), a reference voltage
less than 10 volts may be necessary to obtain the full ana-
log output voltage range.
2.4 Bipolar Output Voltage with a Fixed Reference
The addition of a second op amp to the previous circuitry
can be used to generate a bipolar output voltage trom a
fixed reference voltage. This, in effect, gives sign signifio
cence to the MSB of the digital input word and allows two-
quadrant multiplication of the reference voltage. The polarity
of the reference can also be reversed to realize full 4-qued-
rant multiplication: AVmrx tDigital Code--- iVOUT. This
circuit is shown in Figure 9.
This configuration features several improvements over ex-
isting circuits for bipolar outputs with other multiplying
DACs. Only the offset voltage of amplifier 1 has to be nulled
to preserve linearity of the DAC. The offset voltage error of
the second op amp (aithough a constant output voltage er-
ror) has no effect on linearity. it should be nuiied only it
absolute output accuracy is required. Finally, the values of
the resistors around the second amplifier do not have to
match the internal DAC resistors, they need only to match
and temperature track each other. A thin film 4~resistor net.
work available from Beckman Instruments, Inc. (part no.
694-3-R10K-D) is ideally suited for this application. These
resistors are matched to 0.1% and exhibit only 5 pprnPC
resistance tracking temperature tttxtttieient. Two of the four
available 10 kn resistors can be paralleled to form R in
Figure g and the other two can be used independently as
the resistances labeled 2R.
2.5 Zero Adjustment
For accurate conversions, the input offset voltage of the
output amplifier must always be nuiied. Amplifier offset er-
rors create an overall degradation of DAC linearity.
The fundamental purpose of zeroing is to make the voltage
appearing at the DAC outputs as near OVDc as possible.
This is accomplished for the typical DAC- op amp connec-
tion (Figure P) by shorting out Rm, the amplifrer feedback
resistor. and adjusting the Vos nuiiing potentiometer of the
op amp until the output reads zero volts. This is done, of
course, with an applied digital code of all zeros if Iour, is
driving the op amp (all ones for Iowa). The short around
Rm is then removed and the converter is zero adjusted.
DAC0830 Series Application Hints (Continued)
cc OP Am c t,
cc) u p c (o to Full Scale)
m LF356 22 pF 4 ps
2t, - LF351 22 pF 5 p.s
van o-- oncosao mm > $611 + Csmv 35. -o LF357* 10 pF 2 #5
I‘m" + "2.: kn RESISTOR ADDED FROM-INPUT TO
l - GROUND TO Insune STABILITY
2 FIGURE 8
(DIGITAL CODE- 128)
OUT REF 128
TL/HI5608-to
IDEALVou-r
MSB .......... LSB + VREF - VREF
1 1 1 1 1 1 1 1 VREF--ILSB -NnEFl+1LSB
1 1 0 o O O 0 0 VREF/2 _|VREFl/2
1 o o o o o o o o 0
01111111 --ILSB +1LSB
0 0111111 -tiE-'il-ILsB ll/RZLFI+1LSB
o o o o o o o -lvnErl +llmErl
'THESE nsssrons ARE AVAILABLE FROM
BECKMAN msrnuuams. me. As THEIR
PART NO. ssm-mox-o
FIGURE 9
2.6 Full-Scale Adjustment
In the case where the matching of Rib to the R value of the
R-ZR ladder (typically 10.2%) is insufficient for full-scale
accuracy in a particular application, the VREF voltage can be
adjusted or an external resistor and potentiometer can be
added as shown in Figure 10 to provide a fulI-scaie adjust-
The temperature coefficients of the resistors used for this
adjustment are an important concern. To prevent degrada-
tion of the gain error temperature coefficient by the external
resistors, their temperature coefficients ideally would have
to match that of the internal DAC resistors. which is a highly
impractical constraint. For the values shown in Figure 10, if
the resistor and the potentiometer each had a temperature
coefficient of k100 ppm/°C maximum, the overall gain error
temperature ooefticent would be degraded a maximum of
0.0025%/"C for an adjustment pot setting of less than 3%
of be.
2.7 Using the DAC0830 In a Voltage Switching
Cortflgumtlon
The R-2R ladder can also be operated as a voltage switch-
ing network. In this mode the ladder is used in an inverted
manner from the standard current switching configuration.
The reference voltage is connected to one ot the current
output terminals (IOUT1 for true binary digital control, town
is for complementary binary) and the output voltage is taken
from the normal VREF pin. The converter output is now a
voltage in the range from 0V to 255/256 VREF as a function
of the applied digital code as shown in Figure 11.
DIGITAL
1lser loan
o-- MGM
TL/Hlsaoa-tt
FIGURE 10. Adding Full-Scale Adjustment
f"" FULL SCALE ADJUSTIENT
mo "J08tttMt
itm AI? Vex AN.)
ZEBOOVG/ l-SBOOVG/OEBOOVO
DAC0830/DAC0831/DA00832
DAC083O Series Application Hints (Continued)
Wm) B I
W‘ 'qu 'ti-ii-me
Mm) :3 +2.55; '8rEttt3ttX
(lam) "
TLIH/5608-12
FIGURE M. Voltage Mode Swllchlng
This configuration offers several useful application atNan-
tages. Since the output is a voltage, an external op amp is
not necessarily required but the output impedance of the
DAC is fairly high (equal to the specified reference input
resistance of 10 kn to 20 kn) so an op amp may be used
for buffering purposes. Some of the advantages of this
mode are illustrated in Figures 12, M, " and M.
There are two important things to keep in mind when using
this DAC in the voltage switching mode. The applied refer-
ence voltage must be positive since there are internal para-
sitic diodes from ground to the Iou-n and koura terminals
which would turn on if the applied reference went negative.
There is also a dependence of conversion linearity and
31 t £01353 1 Um = +t.sei-lla,)(,'s'r)
I mi - . "
- i12-
t Voltage switching mode eliminates output signal inversion and thereiora a
need far a negative power supply.
. Zero code output voltage is limited by the low level output saturation voit-
age of the op amp. The 2 kn pdl-down resistor helps to reduce this volt-
. Vos of the op amp has no effect on DAC Iinean'ty.
FIGURE 12. Single Supply DAC
gain error on the voltage difference between VCC and the
voltage applied to the normal cunent output terminals. This
is a result of the voltage drive requirements of the ladder
switches. To ensure that all 8 switches turn on sutficientty
(so as not to add tsignificant resistance to any leg of the
ladder and thereby introduce additional linearity and gain
errors) it is recommended that the applied reference voltage
be kept less than +5VDC and Vcc be at least 9V more
positive than VHEF. These restrictions ensure less than
0.1% linearity and gain error change. Figures M, 17 and 18
characterize the effects of bringing vast: and Vcc closer
together " well as typical temperature performance of this
voltage switching txonriguration.
TLfH/5608-"
oSltrwetgandsetNnqtirnetorafu8 seahroutputcNm9els =13»:
FIGURE 13. Obtaining a Bipolar Output from a Fixed
Reference with a Slngle Op Amp
DAC0830 Series Application Hints (Continued)
"hers'-'? - AV=+0
FIGURE 14, Blpolar Output with Increased Output Voltage Swing
"Ht -10v Ar m < +1045)
CODE 10)
tt TL/H/5608-14
. Only a single +15V supply required
. Nttnmtetacthm Ml-scale and zero coda output adjustments
. VMAX and VmN must be s +5VDC and 20V.
. lnemmenial Output Step = k, (VMAX - VMIN)-
_ "-isisivuAx -VMo0 + EVMIN
FIGURE 15. Single Supply DAC with Level Shift and Span-
Adjustable Output
Gain and Linearity Error Gain and Linearity Error Gain and Llnearity Error
' ' Variation vs. Supply Voltage 0 4 Variation vs. Reference Voltage Varlation vs. Temperature
. . 0.100 vomai MODE 050mm I
t " dl-l', I 0.015 011mm £11m "s....
F " he.-.. . - g " wuwm F 0.000 lh--.-'st, hy---"
ir,' " Ell?“ ir, m:nv, httr--t.58 ‘><( ""'
tt tt Ag =1zv g 0.025 I /
tli ili gi /
E o E o = ,
- " 025 w _ N
il g " t . mm mm
-0.t . -0.000 u=10mvm=sv thi-
kg,” " 000m mun " Ike =1zv. Wer =2.0v
w” m i i i I
HM 4.0 -oAtn
' 200010121010 0 2 0 0 8 10 -g8-M-1sst$qsM68tttstts
As supp" young thd thr, 'trtltDltle mum lhel Ta, AIIIENY TEMPERATURE ('6)
TL/H/5608-15
FIGURE " FIGURE " FIGURE "
Non: For these curves. VREF 10 the volmgo 0p-
piled to pin 11 (loun) with pin 12 (IOUTZ)
wounded.
ZSBOOVG/ L8800VG/08800V0
DAC0830/DAC0831/DA00832
DAC0830 Series Application Hints (Continued)
2.8 MlstNglanttttutt Application Hlnts
These converters are CMOS products and reasonable care
should be exercised in handling them to prevent catastroph-
ie failures due to static discharge.
Conversion accuracy is only as good as the applied refer-
ence voltage so providing a stable source over time and
temperature changes is an important factor to consider.
A "good" ground is most desirable. A single point ground
distribution technique for analog signals and supply returns
keeps other devices in a system from affecting the output of
the DACs.
During power-up supply voltage sequencing, the -15V (or
-12V) supply of tho op amp may appear first. This will
cause the output of the op amp to bias near the negative
supply potential. No harm is done to the DAC, however, as
the on-chip 15 kn feedback resistor sufficiently limits the
current flow from IOUTI when this lead is internally clamped
to one diode drop below ground.
Careful circuit construction with minimization of lead lengths
around the analog circuitry, is a primary concern. Good high
frequency supply decoupling will aid in preventing inadver-
tant noise from appearing on the analog output.
Applications
DAC Controlled Amplifier (Volume Control)
DIGITAL
INPUTS
-VIN (256)
o Vour = _B_._
. When D--0, the ampl6ar will go open loop and the output will saturate.
. Feedback impedance from the -input to the output varies from 15 kn to
=6 as the Input code changes trom tull-scale to zero.
Overall noise reduction and reference stability is of particu-
lar concern when using the higher accuracy versions, the
DAC0830 and DAC0831, or their advantages are wasted.
3.0 GENERAL APPLICATION IDEAS
The connections for the control pins of the digital input reg-
isters are purposely omitted. Any of the control formats dis-
cussed in Section 1 of the accompanying text will work with
any of the circuits shown. The method used depends on the
overall system provisions and requirements.
The digital input code is referred to as D and represents the
decimal equivalent value of the 8-bit binary input, for exam-
Binary Input
Pln 13 Pln , D
MSB LSB Decimal Equivalent
1 1 1 1 1 1 1 1 255
1 o o 0 0 0 0 0 128
o 0 o 1 0 ll o 0 16
0 0 0 0 0 0 1 0 2
0 o 0 0 o 0 0 0 0
Capacltanoe Multlpller
h LF353
tte ham
TL/H/5608-16
‘Ceouw=01 (1+?)
. Maximum voltage across the equivalent capacitance is
Vo MAX icp amp)
limited to
. Ca is used to improve settling time of op amp.
Applications (Continued)
Variable to, Variable tto, Constant BW Bandpass Filter
TUH/5608-17
" 255_ _ KD(2RQ+RJ_ - Ra(k+1)
ofo wn.c'°° V256 Rdx+1)'3db8w 21rR1C(2Ro+m)
whsrac1=cz=C;K=?andR1 ---RofDAC-- 15k
'Ho=1fOme= R4--R,
.Rattgtrotfoandt2is = "ttt1forttireuitshitWn.Ths
range can be extended to 255 to 1 by replacing R1 with a
second DAooeao driven by the same digital input word.
. Maximum to X a product should be $200 kHz.
DAC Controlled Functlon Generator
AHPUTUDE
smumv/
wmsum/
" mauve
N oumn
TLI HISGOB- 1 B
. DAC control: the frequency of sine, square, and triangle outputs.
" forVoMAx = VoutNofequarBwave outputand R, " 3R2.
- memos
.2ti6tto1llrtearfmqsencyrarxre;osei1atorst-ttttD - o
o Trim symmetry and wave-shape for minimum sine wave distortion.
ZEBOOVG/ I-SBOOVG/OSBOQVO
DACO830IDAC0831/DAC0832
Applications (Continued)
Two Termlnal Floating 4 to 20 mA Current Loop Controller
tit u memo
melwmmm _
TL/H/5608-19
I -- V - + --- 1 + -
OUT REF Ci-, 256 c] [ Rs
. DAOOBSO linearly controls the current flow from the input terminal to the
output terminal to be 4 mA (for D=O) to 19.94 mA (tor D=255).
. Circuit operates with a terminal voltage differential of 16V to 55V.
. P2 adjusts the magnitude ot the output current and p, adjusts the zero
to futl scale range of output current.
. Digital inputs can be supplied from a processor using opto isotators on
each input or the DAC latches can tlorrthrough (connect control lines to
pins 3 and 10 of the DAC) and the input data can be sat by SPST toggle
switches to ground (pins 3 and 10).
DAC Controiled Exponential Tlrne Response
Va: loun
-r VnuAL
- VIN meAL
10k - mm. A
n 255 , a m tt AND ,
V = i-spout - At0+ iii"
TL/H/5608-20
. Output responds exponentially to input changes and automatically stops
when Pour - VIN
. Output time constant is directly proportional to the DAC input code and
capacitor C
. Input voltage must be positive (See section 2.7)
Ordering Information
Temperature Range 0''C to + TO' -40'C to + 85'tt -55'C to + 125°C
Non 0.05% FSR DAC0830LCN DAC0830LCM DAC0830LCV DAC0830LCJ DACOBSOLJ
Linearity 0.1% FSR DAC0831LCN
0.2% FSR DAC0832LCN DAC0832LCM DAC0832LCV DAC0832LC0 DA00832LJ
Package Outline N20A-Moided DIP M208 Small Outline V20A Chip Carrier J20A-Cerarnitt DIP
ZSBOOVO/ l8800V0/08800VO
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