DAC0630CCD ,4.5 to 5.5 V, triple 6-bit video DAC with color paletteElectrical Characteristics
+5V, unless otherwise specified. Boldface Ilmlts apply for Tum to Tua ..
DAC0631CCD ,4.5 to 5.5 V, triple 6-bit video DAC with color paletteFeatures
I Pixel rates of 50 MHz (DAC0630) and 35 MHz
(DAC0631)
I 256 x 18 bit color palette ..
DAC08 ,8-Bit high-speed multiplying D/A converterSpecifications subject to change without notice.1ABSOLUTE MAXIMUM RATINGS 2Package Type UnitJA ..
DAC-08 ,8-Bit high-speed multiplying D/A converterapplications, the outputs can be directly converted toComplementary Current Outputsvoltage without ..
DAC08. ,8-Bit high-speed multiplying D/A convertercharacteristics refer to both I and .)OUT OUT DAC08A/H DAC08E DAC08CParameter Sy ..
DAC0800 ,8-Bit D/A Converterapplications while the nonlinearitiesYHigh output compliance b10V toa18Vof better than g0.1% over t ..
DK1A-5V , MINIATURE POWER RELAY
DK1A-L2-3V , MINIATURE POWER RELAY
DK2A-5V , 1a 10A, 1a1b/2a 8A small polarized power relays Switching power supply
DL207 , SILICON RECTIFIER DIODES
DL207 , SILICON RECTIFIER DIODES
DL207 , SILICON RECTIFIER DIODES
DAC0630CCD-DAC0631CCD
4.5 to 5.5 V, triple 6-bit video DAC with color palette
DAC0630/DAC0631
National
1 Semiconductor
DAC0630/DAC0631
Triple 6-Bit Video DAC with Color Palette
General Description
The DAC0630 and DAC0631 are monolithic triple 6-bit video
digitaI-to-analog converters with on-chip 256 x 18 bit color
palettes and are intended for graphics applications. The col-
or palette makes possible the display of 256 colors selected
from a total of 256K possible colors through the internal
6-bit video DACs. The DACs are capable of driving 75n or
37.50 loads to normal video levels at pixel rates of 50 MHz
(DAC0630) and 35 MHz (DAC0631). The DAC0630 and
DAC0631 provide a bidirectional microprocessor interface
with TTL compatible inputs. The DAC0630 and DAC0631
are pin- and tunctionally-compatible with the lnmos IMS
6171-50 and IMS G171-35 and IMS G176-50 and IMS
G176-35.
Features
:1 Pixel rates of 50 MHz (DAC0630) and 35 MHz
(DAC0631)
I: 256 x 18 bit color palette
u 256K possible colors
a Color palette read-back
I: Three internal 6-bit DACs
n Directly drives (75tt) video cable
I! RGB analog output
" Composite blank
a Single +5V supply
" Low power, high performance CMOS/bipolar
processing
a TTL compatible inputs
" Full asynchronous pP interface
I: 28-pin package
Block and Connection Diagrams
Dual-ln-Llne Package
PCLK , altltt 4 .e RED- I 0 28 "-y
mm! or
GREEN- 2 27 -fls,
A-tmo BLUE- 3 26 -lts,
less- 4 25 .-yt7t
Color Palette Pa- 5 " _D7
256118 Bit th- 6 23 -os
Po-P7 ) unch And Address P2- 7 DAcoeso 22 -05
Ps- 11 18 -th
t y 18 PCLK-113 " -au1m<
Do - By 3-511 -
MI GND-1 14 15 -Ri)
WR-r Proc -FltEt)
Ro--' i,','d,',12'f Triple TL/H/9638-2
ii-im - GREEN Top Vlew
ttso--' 18-im Data Latch 18 ) DAG
RS‘ -. - BLUE Order Number
DAC0630CCD DAC0631CCD
" " See NS Package Number D28D
BLANK-
IREF Order Number DACOGS1CCN
See NS Package Number N283
TL/H/9636-1
Absolute Maximum Ratings (Notes1&2)
ll MltltttrWAtrrospatre ttptrttlmstt devices are required,
please contact the Nntlonal Semlconductor Sales
OffltNtfDlatrittutttra for availability and specifications.
Positive Supply Voltage (V+) GND - 0.3V to 7V
Voltage at Logic Inputs (Note 3) GND - 0.5V to
V+ + 0.5V
Voltage at Analog Pins 1-4 (Note 3) GND - 0.5V to
V+ + 0.5V
Analog Output Current, Pins 1-3 45 mA
Reference Current, Pin 4 15 mA
DC Digital Output Current (Note 4) 25 mA
Power Dissipation (Note 5) LOW
ESD Susceptability (Note 6) 2000V
Soldering Information
D Package (10 sec) 300°C
N Package (10 see) 260°C
Storage Temperature - 65°C to 1 50°C
Operating Ratings (Notes1&2)
Temperature Range
TMIN g TA S TMAX
Positive Supply Voltage
0°C s; TA 3 + 70°C
4.5 to 5.5V
AC and DC Electrical Characteristics
The following ttpeaTieations apply for V+ = +5V, unless otherwise specified. Boldface limits apply tor Tum to TMAX: all
other limits TA = 25°C.
DAC0630
DAC0631
Symbol Parameter Cttttdltlotttt Tested Dealgn Unlts
Typlcal
(Note n leIt Limit
(Note 8) (Note 9)
IREF Reference Current Minimum - 3 mA
Maximum - " mA
IAVE Maximum Average DA00630 PCLK = 50 MHz 160 mA
Supply Current DAC0631 PCLK = 35 MHz 1 so mA
IREF = 10 mA
Digital Outputs Unloaded
VREFmin Minimum Reference Voltage at V+ = 4.5V If + - tt V
'REF Pin IREF = 8.88 mA
IIN Maximum Digital lnputCurrent V+ = 5.5V i " A
(Pins 5-13,15,16,25-27) GND s; vm s v+ "
loz Maximum Tri-State Digital Output V+ = 5.5V 1 " A
Current (Pins 17-24) GND s VIN s v+ "
VOH Minimum Logic"1"Output V+ = 4.5V, lo = -5 mA
Voltage
VOL Maximum Logie"0"Output V+ = 4.5V, IO = +5 mA
Voltage
Vm Minimum Logic "1" Input Voltage 4.5V s: V+ s 5.5V 2 V
" Maximum Logic "ty' InputVoItage 4.5V S V+ g 5.5V 0.8 V
DAC Resolution 6 Bits
VOUT Minimum Output Voltage IOUT g 10 mA 1 5 V
Compliance (Pins 1-3) .
ISQOOVCl/OSSOOVCI
DACOB30/DACOB31
AC and DC Electrical Characteristics (Continued)
The following specifications apply for V+ = + 5V, unless otherwise specified. Boldface limits apply tor Tum to Twut; all
other limits TA = 25'C.
DACOB30
DA00631
Symbol Parameter Conditions Tested Design Units
Typlcal
(Note n leIt Limit
(Note 8) (Note 9)
low Maximum Output Current VOUT 3 1V 2 , mA
Compliance (Pins1-3) IRE; S 10 mA
Full-Scale Gain Error 2L =r. 750 + 30 pF --8, +2 %
(Note IO) IREF = 4.44 mA
A. = 37.5n +' 30 pF -14. -4 %
IREF = 8.88 mA
DAC-toDAC Mismatch 2L = 75tt + 30 pF
'REF = 4.44 mA " %
(See Note 11)
Integral Non-Linearity ZL = 75n + 30 pF
(Note 12) IREF = 4.44 mA i0.5 LSB
toN Rise Time 2L = 75n + 30 pF 8 ns
(Note 13) IREF = 4.44 mA
Maximum Full-Scale DAC0630 h. = 75ft + 30 pF tio ns
Settling Time DAC0631 IREF = 4.44 mA 28 ns
(See Note 14)
Maximum Glitch Energy ZL = 75ft + 30 pF
IREF = 4.44 mA 1200 i400 pV-sec
(See Note 15)
Cm Digital Input Capacitance (Pins 7 F
5-13, 15, 16, 25-27) p
COUT Digital Output Capacitance (Pins W = Logic High 7 F
17--24) p
Cog” Analog Output Capacitance BLANK == Logic Low
. 10 pF
(Pins 1-3)
VOUTBLANK Maximum Blanking Output BLANK = Logic Low
Voltage ZL == 75tt + 30 pF 10.5 LSB
'REF = 4.44 mA
Unadjusted OutputOffsot Error BLANK --.. Logic High
il. = 75n + 30 pF $0.5 LSB
IREF = 4.44 mA
Clock Feedthrough DAC0630D PCLK = 50 MHz -30 dB
(Note 16) DAC0631D POLK = 35 MHz -35 dB
DACO631 N PCLK = 35 MHz -30 dB
2L = 75n + 30 pF
IREF = 4.44 mA
PSS Power Supply Sensitivity 4.5V g V+ S 5.5V
IOUT = Full Scale 6 %/V
ZL == 750 + 30 pF
'REF = 4.44 mA
AC Electrical Characteristics The following specifications apply for V+
Tum to TMAX; all other limits TA = 25°C. Design Limits apply for 4.5V s V+ s: 5.5V.
= + 5V. Boldtace Ilmlts apply for
DAC0630 DACOGM
Symbol Parameter Conditions Typical Tested Design Typical Tested Design Unlts
(Note 7) Llmlt lelt (Note n Limit Limit
(Note 8) (Note 9) (Note 8) (Note 9)
tCHCH Minimum PCLK Period 20 20 28 " ns
AtCHCH Maximum PCLK Jitter (Note 17) i 2.5 k2.5 %
ICLCH Minimum PCLK Width Low 6 6 9 tt ns
tCHCL Minimum PCLK Width High 6 6 7 T ns
IPVCH Minimum Pixel Word Setup Time (Note 18) 4 4 4 4 ns
ttyex Minimum Pixel Word Hold Time (Note 18) 4 4 4 4 ns
tBVCH Minimum BLANK Setup Time (Note 18) 4 I 4 4 ns
tCHBX Minimum BLANK Hold Time (Note 18) 4 4 4 q ns
[CHAV PCLK to Valid DAC Minimum (Note 19) 5 s 5 S ns
Output Maximum 30 so 30 so
AtCHAV Maximum Differential Output (Note 20)
1 1 ns
tWLWH Minimum WA Pulse Width Low 50 tut 50 BO ns
tRLRH Minimum Am Pulse Width Low 50 so 50 so ns
tSVWL Minimum Register Select Setup (Write Cycle) 1 0 , o 1 5 1 s ns
. . R .
tSVRL Minimum eglster Select Setup (Read Cycle) 10 , o 1 5 , s ns
tWLsx Minimum Register Select Hold (Write Cycle) 10 1 o 15 , 5 ns
tRLSX Minimum Register Select Hold (Read Cycle) 10 " 15 " ns
tDVWH Minimum Wm Data Setup Time 10 1 tt 15 1 s ns
thDx Minimum Tm Data Hold Time 10 1 o 15 1 s ns
tRLQx Minimum Output Turn-On Delay 5 s 5 5 ns
tRLtav MaXImum RD Enable Access 40 att 4O " ns
tRHax Minimum Output Hold Time 5 5 5 tt ns
th02 Maximum Output Tum-Off Delay (Note 21) 20 20 20 20 ns
t Minimum Successive Write
WHWLI Interval 3(tCHCH) aqtcncn) 3(t0HCH) 3(fcncn)
t Minimum iiim followed by Read
WHRLI Interval 3(1CHCH) attersttro 3(ICHCH) Btterauo
t Minimum Successive Read
RHRLI Interval 3(tCHCH) atttmtno 3(tCHCH) ttttemeso
t HW Minimum W5 followed by Write
R LI Interval 3(tCHCH) 360mm) 3(tCHCH) 3(tcucu)
tWHWL2 Minimum WA- after Color Write (Note 22) 3itCHCH) 3(tchH) 3&0”) attcsatro
lEQOOVO/OSQOOVG
DACOB30/DAC0631
AC Electrical Characteristics (Continued) The following specifications apply tor v+ =
limits apply for TMIN to TMAX; all other limits TA = 25°C. Design Limits apply for 4.5V s V+ 3 5.5V.
+ 5V. Boldface
DAC0630 DACOG31
Symbol Parameter Conditions Typical Tested Design Typical Tested Design Units
(Note n Limit Limit (Note n Limit lelt
(Note 8) (Note 9) (Note 8) (Note 9)
tWHRLZ Minimum FIE after Color Write (Note 22) 3(tCHCH) attereeto 3(‘CHCH) Sttersttto
tRHRLS? Minimum E after Color Fiead (Note 22) 6(tCHCH t$ttetetttn 6(‘CHCH) htemttrn
tRHWLZ Minimum W after Color Read (Note 22) 6ittyarro Ihtetatro 6(tCHCH) 1tttemno
tWHRLa Minimum FT) after Read (Note 22)
Address Write 66mm) 6(fcmnn G(ICHCH) 6(*cmm)
eaxinym Iti"'/ Read Enable so so ns
Transition Time
Note 1: Absolute Maximum Ratings indicate limits beyond which damages to the device may occur. DC and AC electrical spkttieatitms do not apply when operating
the device beyond its spaeitied operating ratings.
Note 2: All voltages are measured with respect to ground, unless othenwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (Vm < GND or VIN > V+) the absolute value of current at that pin should be limited
to 5 mA or less. The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mA.
Note 4: One output at any time. The maximum time for this output level is one second
Note 5: The maximum power dissipation must be aerated at elevated temperatures and is dictated by Taser, 9M. and the ambient temperature, TA. The maximum
aliowable power dissipation at any temperature is PD - (TJMAx-TploJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX = 125‘0, and the typicat thermal resistance (9.110 of the DAC0630f0631 000 when board mounted is 4trC/W. The typical theme! resistance for the
0A00630/63100N when board mounted is 65’C/W. .
Note 6: Human body model. 100 pF discharged through a 1.5 kn resistor.
Note P. Typicats are at 25'C and represent most likely parametric norm.
Note tk Tested limits are guaranteed to National's AOQL (Avetage Outgoing Quality Level).
Note 9: Design limits are guaranteed to Nationai's AOQL (Average Outgoing Quality Level) but not 100% tested.
NM. Ith Full-Scale Gain Error is dMintrd as [[(F.S. IouT)RL-Z.1(IREF)Rl]/[2.1(IREF)HL] "00%. VBLACK LEVEL = iN.
Note 11: The listed value is relative to the midpoint ot the full-scale disMbutkm of the internal three BAGS.
Note 12: Zero and fuil-scale adjusted linearity error = Nout-Nomot-iD X VLsa)l/VL53, VLSB " (Vtull satkr-VoftsetVe.
Note 13: The rise time is measured trom 10% to 90% of the full scale transition.
Note " The output signal's settling time is measured from a 2% change at the transition's initial value until it has settled to within 2% of the final value, excluding
clock tmsdttrough.
Note IP. This value is determlned using triangle approximation: glitch energy = (area of positive transienO-(area of negative transient).
Note 16: The value shown is the ratio ot the RMS value of any PCLK signal on the analog outputs to the tuIl-scale output voltage (700 mV).
Nate " TNs parameter is the allowed variation in the pixel chock frequency. It does not permit the pixel clock period to vary below the mlninum value tor pixel
clock ('CHCH) period speafod above.
Note 18: It is necessaiy that the color palette's pixel address be a valid logic Ievet with the appropriate setup and hold times at each rising edge at Pch (this
requirement indudes the blanking period).
Note " A valid analog output is defined as the 50% point between suwessive values. This parameter is stable with time but can vary between different devices
and may vary with dherent dc operating conditions.
Note Mk This applies to differgttt analog outputs on the same device.
Note " Measured at 1200 mV from initial steady state output voltage.
Note 22: This parameter allows synchronization between operations on the microprocessor interface and the pixel stream being processed by the color palette.
DAC0630/DAC0631
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DACOGSO/DAC0631
Timing Waveforms (Continued)
Wt '""''''H, ,
hm tsnsy
a... RS, At222222227 l Egon.” DOO
N H )0000000 I 0000000000t
)()()()()()00()0000(
a..- 9. 1000t )000( )0000()l
TL/H/9636-6
FIGURE a. main Write Cyele
tsm tass
FIGURE a. Battle Read Cyttle
TLfH/9636-7
temiice
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tesolilglgiiEilg)CzMil Iigldgggg)CCD(g
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FIGURE ti. Write ttt Pixel Emu: Register Followed by a)Wrlte, b)Read
TL/H/9636-il
TL/H/9636-8
FltWRE mm. Read from Plxel Mttttit or Plttel Address
msgiater Among 0.. Write Mode) Followed by Read
FIGURE mu. Read from 1...... Mask or 3.6. >338
Register A125 or Write Eons Followed by Write
Timing Waveforms (Continued)
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FIGURE r. £23 man Read Back Pixel Addretta Rtsglster tRead Mode,
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TL/H /9636- IO
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FTGURE a. Write and Read who: 2.8. Addretts Register (Write Iona.
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TLfHftm36-t2
LSQOOVOIOEQOOVG
DAC063OIDAC0631
Timing Waveforms (Continued)
MMM t22222222r
mm 11020103. f22222222r
Bo-ty, ADDRESS l RED y {cases}
Tl.fH/MM-19
FIGURE 10. Read Color Value then Read pixel Address Hoglstor (Road Mode)
time, W1 ‘wmlu
Rso /)l1000 'tiMlttti “3191910101" t22222l17 -1:
A I I foo, /)()0(XXO
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TL/H I 9636- "
FIGURE 11. Color Value Write Followed by Any Read
tf22222F t2222222flt7
Rs, h K)0()0(h /X)0()0(O /)0000G, ,0000000CCX
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FIGURE 12. Color Value Write Followed by Any Write
DACOG30/DAC0631
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DACOB30/ DACOG31
Connection Diagram
Plastic & Cavity
Dual-In-Une Package
RSD-I 1 o 28 -v
GREN- 2 27 -lts,
BLUE- 3 26 -R50
'ter-" 4 25 -Frrt
Po- 5 24 --h
Pet s 23 -th,
P2- 7 moosso 22 '05
Ps- a tWl063t 21 -tu
Pc- ' 20 -h
Ps- 10 19 -n2
Ps- 11 18 --111
Pr-" 12 17 -ot
ptvt-- 13 16 -BLANK
GND- 14 15 -RT)
TL/H/sssa-IB
Top View
Pin Descriptions
RED (1),
GREEN (2),
BLUE (3)
Inst: (4)
Po-Pr ts- 12)
These are the analog output pins of the
6-bit DACs. The output currents from
these pins flow through the terminating
resistors and develop the RGB (red,
green and blue) voltages that drive the
monitor. Each DAC is composed of 63
current sources. The output of each at
these current sources is summed togeth-
er according to the applied 6-bit binary
value.
This is the Reference Current input. The
current forced out of this pin to ground
determines the current sourced by each
of the 63 current sources in each of the
three 6-bit DACs. Each current source
produces 1/30 of IREF when activated by
the 6-bit digital input code.
These are the high-speed Pixel Address
inputs. This byte-wide information is
latched and masked by the Pixel Mask
Register. The resulting value is used as
an address of a location in the Color Pal-
ette RAM.
PCLK (13)
GND (14)
R_D(15)
Do-Dr (17-24)
WA (25)
Mo, RS,
(26, 27)
V+ (28)
The high-speed Pixel Clock signal is ap-
plied to this pin. The rising edge controls
the latching of the Pixel Address and
Blanking inputs. It also controls the prog-
ress of these values through the three
stage pipeline of the Color Palette and
through the DACs to the outputs.
This is the ground pewer supply connec-
This is the active low Read bus control
signal. When active, any information
present on the internal data bus is avail-
able on the Data l/O lines. Do-Dr.
This is an active low signal that forces the
DAC's outputs to zero. When BLANK is
asserted a video monitor's screen be-
comes black and the DACs ignore any
output values from the Color Palette.
However. the Color Palette can still be
updated through Do-Dr.
These are the bidirectional Data I/O lines
used by the host microprocessor to write
information (using the active low W) into
and read information (using the active low
AB) from the DA00630 and DACO631's
internal registers (Pixel Address register,
Color Value register, and Pixel Mask reg-
ister).
During the write cycle. the rising edge of
WA latches the data into the selected
register.
The rising edge of M determines the
end of the read cycle.
With FTD and W equai to a logic high,
the Data vo lines will no longer contain
information from the selected register
and will go into a tristate mode.
This is the active low Write signal. It con-
trols the timing of the write operations on
the microprocessor interface inputs, Do-
th. When active, any information present
on the external data bus is available to
the Data l/O lines, Do-D7.
These are the Register Select lines which
control the selection of one of the three
internal registers. These two lines are
sampled during the falling edges of the
enabie signals (Al5 or W). See Func-
tional Description for more information re-
garding the internal registers.
This is the positive supply pin. It is nor-
mally connected to +5 Vdc and by-
passed with a 10 pF tantalum capacitor
and a 0.t p.F chip capacitor.
Functional Description
The DAC0630 (or DAC0631) forms the output stage for high
resolution raster scan RGB video systems. It contains a Col-
or Palette with 256 memory locations that are 18 bits wide.
The color palette’s output is connected to three high speed
current output 6-bit video DACs. The devices use on-board
registers to interface easily with microprocessors.
MICROPROCESSOR INTERFACE
The DACOGSO and DAC0631's microprocessor interface
consists of three internal registers; Pixel Address register,
Color Value register, and Pixel Mask register. These are in-
dividually accessed by register select signals, RSo and RS1.
The following table defines which of the three internal regis-
ters is selected by each of the tour combinations of logic
states of RSo and RSI.
RS, Reglster
0 0 Pixel Address (Write Mode)
1 1 Pixel Address (Head Mode)
Color Value
0 Pixel Mask
The contents of the color palette can be accessed through
the Color Value and Pixel Address registers.
All of the operations on the microprocessor interface can
take place asynchronously to the pixel information currently
being processed by the Color Palette.
The Pixel Address register is a byte-wide latch that rw
ceives and latches address information applied to pins IT-
24. It can be used in either the Read and Write mode de-
pending on the logic state of RSo and RS1. With RSo =
RS1 = 0 (register select = 0,0), the Pixel address register
is in the write mode. Two events normally precede writing
one or more new color definitions to the color palette. The
first is the specification of a color palette address. Second,
the Color Value register must be loaded with a color dtarini-
tion. The sequence of data transfer is 1) the desired color
palette address (this address is stored in the Pixel Address
register) and 2) the color definitions: red, green and blue.
Refer to Figures " and M.
When R80 = RS1 = 1 (register select = 1,1), the Pixel
Address register is in the read mode. Once again, two
events take place and normally precede reading one or
more color definitions in the color palette. The first action is
to specify an address within the color palette. the second is
to load the Color Value register with the contents of the
color palette location whose address is stored in the Pixel
Address Register. The color definition data transfer se-
quence is md, green and blue. Refer to Figures to, 13 and
The Color Value register is an internal 18-bit wide register
used as a buffer between the microprocessor interface and
the color palette. It is accessed by setting RSO = 1 and
RS1 = 0. A color dtafinition can be read from or written to
this register by a sequence of three byte-wide transfers to
this register address. When a byte is written to this register,
only the least significant six bits (00-05) contain color infor-
mation. When a byte is mad from this register address, only
the six least significant bits contain information-the most
significant two bits am set to zero. Refer to Figures fo- 14.
After the write sequence is completed, the Color Value reg-
ister’s contents are written to the sptmified color palette ad-
dress stored in the Pixel Address register. Finally, the Pixel
Address register is automatically incremented.
It is possible to read the color definitions stored in the
DAC's color palette. After setting RSo and RS1 equal to 1,
the desired color palette address is stored in the Pixel Ad-
dress register. The color definition (18-bits) in the desired
color palette location is then automatically transferred to the
Color Value register and me Pixel Address is auto-incre-
mented. With successive read cycles. the color dMinitkms
pointed to by the incremented address are transferred to
the color value register. Refer to Figure 13.
Tho Pixel Mask register is a byte-wide latch. by setting
RSo = 0 and RS1 = 1, the Pixel Mask register can be
accessed by the microprocessor interface, Do-Dr This reg-
ister is used to mask selected bits of the pixel address val-
ues applied to the Pixel Address inputs (Po-P7). A "1" in
any location in the Pixel Mask register leaves the corre-
sponding bit in the pixel address unchanged. A "o" will reset
the corresponding bit to zero. The operation of the Pixel
Mask register does not affect the address of the color tityfi.
nition when the microprocessor accesses the color palette.
The masking operation makes it possible to alter the dis-
played colors without altering the contents of external video
memory or the DAC0630/631's color palette.
WRITING TO THE COLOR PALETTE
A new color definition can be stored in the color palette by
first specifying the initial address while in write mode
(RSo = RS1 = WA = 0).This address is stored in the Pixel
Address register. The initial address is followed by the md,
green and blue color definition data (R80 = 1, RS1 =
WR = 0). These three six-bit values are collected together
in the Color Value register for a total of 18 bits. The internal
logic then transfers this new color definition to the location
pointed to by the address stored in the Pixel Address regis-
tar. As soon as this transfer is completed, the Pixel Address
register is auto-incremented. This allows consecutive color
palette locations to be updated without the microprocessor
specifying each address. All that is necessary is to continue
supplying the red, green and blue data for each consecutive
address. Refer to Figures 11 and M.
Attempting to update the color palette when BLANK is not
asserted results in the data from the Color Value register
taking precedence over the DAC0630 and DAC063rs bit
mapping operation. The output of the three 6-bit DACs will
be based on the color definition from the memory location
specified by the pixel address register and not the address
found on Po-P7. This conflict results in the DACS generat-
ing unexpected output levels. This can last as long as two
PCLK periods.
READING FROM THE COLOR PALETTE
To read a location in the color palette an address is sent on
the Data l/O lines (00-07) while in read mode (R30 ==
RS1 = 1, WA = 0) and stored in the Pixel Address register.
The color definition in the speaTisrd color palette tocatlon is
then transferred to the Color Value register and the Pixel
Address register is auto-incremented. The color definition
can now be retrieved with three sequential read operations
(RSO = 1, RS, = AT5 = 0). The first byte placed on the
Data l/O lines contains the red value. The next is green,
and the last is blue. The two most significant bits are set to
zero in each case. Once again, the Pixel Address register is
auto-incremented, and consecutive color palette locations
can be read simply by specifying the beginning address and
reading the color palette one or more times. Refer to Fig-
ures 10, " and 14.
ISQOOVO/OSQOOVCI
DA00630/DA00631
Functional Description (Continued)
If the Pixel address register is ever updated during a read or
write operation, the current data sequence is terminated
and a new read or write operation is initialized.
VIDEO PATH
The video path consists of the Pixel Latch and Mask (inputs
Po-Pr), color palette (256 x 18-bit wide RAM), 18-bit wide
bus, and an 18-bit wide latch on the inputs of the three 6-bit
high-speed video DACs. Tho video path uses a three clock
cycle (PCLK) pipeline for the pixel address and BLANK in-
puts. These signals are latched on the rising edge of PCLK.
At each rising edge of PCLK, the Color Palette address ap-
plied to Po-Pr is stored in the Pixel Latch and defines a
location in the Color Palette. The color definition in that lo-
cation is then transferred to the three 6-bit DAC input latch-
ANALOG OUTPUTS
The analog outputs are designed to drive 75n loads with
IREF set to 4.44 mA or 37.5O loads with lag; set to
8.86 mA. For both loads the peak-white amplitude is 0.7V.
The analog outputs can be set to zero by using the BLANK
input. This is an active tow signal that forces the analog
outputs to ground by placing all zeros on the DACs' inputs.
The color definition selected by the pixel address is ignored.
The DAC0630/631's DACs use switched current sources
that are summed together, thus generating the output cur-
rent Each 6-bit DAC consists of 63 current sources, each of
which has a magnitude of IREF/30. The digital input code
determines the number of current sources that are active
and contributing to the total output current. This output cur-
rent; in coniunction with a termination resistance connected
between each DAC output and ground, sets the tull-scale
magnitude of the output voltage as determined by
VPEAK WHITE = 2-1(|REF)RL
VBLACK LEVEL = 0V
Application Hints
POWER SUPPLY
The DACO630 and DAC0631 draw large transient currents
from the power supply. To ensure proper operation it is nec-
essary to utilize standard high frequency board layout and
power supply distribution techniques.
The transient currents drawn by the DAC0630 and
DAC0631 dictate that the ac impedance at the supply pins
must be kept to a minimum. This is accomplished by using
the recommended decoupling capacitors, C1 and C2, as
shown in Figure M. These capacitors must have leads that
are as short as possible. High frequency decoupling is ac-
complished with a 0.1 pF chip capacitor, Cr A bead tanta-
lum, between 10 pF to 47 WF, should be used for C2.
Differential ground noise can be created when a voltage
difference appears between pin 14 and the ground of the
digital devices driving the DAC0630 or DAC0631. This volt-
age difference is caused by series impedance in the ground
path and the current transients drawn by the DACOG30 or
DAC0631. The differential ground noise can be minimized
by using large, low inductance ground paths between the
digital devices that drive the DA00630 or DAC0631 and pin
14. Therefore, a ground plane layout is recommended.
ANALOG OUTPUT-UNE DRIVING
The connection between the DAC's outputs and the RGB
inputs of the video monitor it is driving should be viewed as
a transmission line. Impedance changes along this line will
result in the reflection of part of the video signal back to the
DAC's outputs. These mfieetitms may result in a degrada-
tion of the picture quality displayed on the monitor.
To ensure good signal fidelity, RF techniques should be ob-
served. Any traces connecting the DACOGSO or DA00631 to
an on-board connector should tom a transmission line of
75ft impedance. However, the need to ensure that the con-
nothing traces form a transmission line can be eliminated by
placing the DAC's output termination resistors at the output
connector instead of the DAC's output pins.
The coaxial cable that connects the DAC's outputs to a vid-
eo monitor should have a characteristic impedance of 750.
Connectors on the coaxial line can cause impedance
change. Any connectors used with the coaxial cable should
match its characteristic impedance.
There are tour different methods of terminating the DAC
outputs:
1) Single termination at the DAC (750)
2) Single termination at the destination (750)
3) Double termination (37.5tt)
4) Buffered signal
1) Single termination at the source involves placing a sin
gle termination resistor at each DAC output of the DACO630
and DAC0631 (or at the connector, as described above). No
other terminating load is present. Therefore, a high-input
impedance monitor should be used. The ac load driven by
the DAC's outputs is the transmission line impedance in par-
allel with the load resistor. The transmission line's imped-
ance should match the impedance of the load resistor.
Thus, the DAC's output has an initial signal amplitude that is
halt the de value expected. This half-amplitude signal is
100% reflected by the open circuit presented by the monitor
input. This restores the signal amplitude to the expected
value. The reflections from the monitor propagate back
towards the DAC outputs. The load resistor at each DAC
output presents a correctly laminated transmission line so
no further reflections occur. This arrangement is relatively
tolerant to mismatches in the transmission line between the
DAC and the monitor because no tttflectiorts occur at the
DAC end of the transmission line. However, multiple moni-
tors should not be connected in parallel despite each moni-
tor's high input impedance.
2) Single termination at the destination has the lamina-
tion impedance at the input of the monitor acting as both the
load resistor tor the DAC and the termination impedance of
the cable (transmission tine). It the connection between the
DA00630/631 is correctly terminated there will be no reflec-
tions. However, if there are any line impedance variations
along the cable, reflttetitms will occur and create "ghost im-
ages" on the display. This occurs because there is a reflec-
tion from the point where the mismatch occurs back to the
DAC's output. The signal then mtitmts off the DAC's output
back toward the monitor. It arrives with a significant time
delay following the original signal, and "ghosting" results.
3) Double termination of the DAC outputs allow each end
of the transmission line to be correctly matched. This results
in the least amount of rtneetion and the highest signal and
display fidelity. This termination method also allows for the
Application Hints (Continued)
Pixel Address Input)
OOO‘IOUI
D PClK
DACOSSO
OACOBSI
tMt) IL
For IREF= 4.44m:
RI = 22.Ut, R2 = 9310
For IREF = 8.88 nth:
tt1=110,R2--4640
Date Input/output 3
To monitor's RED input.
Bt-Ari-g
Control Signals
CDUIUOM
To monitor's GREEN input.
_ tx""'"-"'")
fr'-'"'-"
PlxelCleck IIIIIII‘I
Note: Bead-styfs tantalum capacitors should be used for the 10 pF devices.
Thermaliy connect the NPN transistors together with a Wakefield 259 series Equalizing Link.
To monitor's BLUE input.
. 1/4 Watt Carbon Film
TL/H/9636-19
FIGURE 15. Typical Connection Showing IREF Generator and Double Termination
fastest fall time. The DAC termination’s RC time constant
sets the outputs' fall time. The greater the time constant,
the slower the fail time. Therefore, the tall time will be mini-
mized since the impedance using this termination technique
is less than that achieved with single termination. With dou-
bie-tennination it is necessary to increase IREF to
8.88 mA to ensure a full-scale output voltage of 700 mV.
4) By placing a buffer at the DAtys output, the DACOBSO
and DAC0631 will be able to drive large capacitive loads
such as long lossy cables. The buffer requries a high input
impedance. a condition that is satisfied with LM1203 FIGB
Video Amplifier System. A 75n load is placed at the buffer's
input. The buffer's low output impedance should be
matched to the interconnecting cable with a series resistor.
The cable should then be terminated with the same resist-
ance at the monitor.
ANALOG OUTPUT-PROTECTION
The DACOGSO and DAC0631 have on-chip electrostatic dis-
charge (ESD) protectlon on each pin. However, the same
precautions should be taken as with any other CMOS inte-
grated circuit during manufacturing to reduce the possibility
of ESD damage.
GENERATING IRE;
An active current source for IRE; is recommended to ensure
that the DACs have predictable and stable output currents.
There are numerous methods available to generate the ref-
erence current. The voltage drop from v+ to the IREF pin
increases with increasing IREF current. The circuit used to
generate 'REF must be designed to operate at the minimum
voltage (VREFmin = V+ - 3V) expected from the tag; pin
to ground. For any application, VREFmin will be smallest
when IREF is maximum and supply voltage is minimum. For
IRE; = 8.8 mA and V+ = 4.5V, the IREF generator will
have to operate with 1.5V or less across it. IREF generators
that require a voltage drop greater than 1.5V may be used if
a negative supply is available.
A simple IRE..- generator circuit is shown with the DAt30630/
DAC0631 in Figure M. As shown, this IRE; generator will
sink Tr.4.44 mA (single termination) with R1 = 22.1n and
R2 = 9310.. For applications that use double termination,
R1 = 110 and R2 = 4640. The diode connected transis-
tor, till, across 02's bese-emitter lunction performs a first.
order compensation for thermal variations. It is important to
keep the lead lengths as short as possible. This will help
reduce stray capacitance and the amount of PCLK that is fed
into the 'REF pin.
ISQOOVG/OESOOVG
DAC0630/DAC0631
Application Hints (Continued)
mm mm InpuH
IN I“.
om hput/Ouepm
hbbkkl
flafig 3:335:95
_. N - n n
control Slgnab
M00630
M60631
m m_nnJ'LrLr
Note: Bead-style tantalum capacitors should be used for the 10 pF devices.
3 ifcr. 0M ttttmitor'a BLUE
is '1/4 tratt urban Fllm
T1.fH/im36-20
FIGURE 16. Single Temlnatlon wlth LM334 Current Source IREF Generator
Figure 16 shows an alternative method of generating IREF.
The LM334 precision current source is used in a tempera-
ture compensated configuration. The reference current is
set by a single tesistor, RI, independent of V+. The cur-
rent's value is
IRE; T.' 160 mV/RI
DECOUPLlNtMrtEF
The magnitude of the current flowing through the internal
current sources depends not only on IRES, but also on the
voltage at pin 4 relative to V+. Therefore, voltage variations
between V+ and the IREF input can result in variations in
the DAC's output current. These variations can be greatly
attenuated by using a high frequency capacitor in parallel
with a larger electrolytic capacitor to couple the IHEF input
to V+.
This datasheet has been :
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
DAC0631CCD - product/da00631ccd?HQS=T|-nu||-nulI-dscataIog-df-pf-null-wwe
DAC063OCCD - product/dacOBBOccd?HQS=T|-nu|I-nulI-dscataIog-df-pf-null-wwe
