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CY7C1366C-166AXC |CY7C1366C166AXCN/a300avai9-Mbit (256 K ?36/512 K ?18) Pipelined DCD Sync SRAM
CY7C1366C-166AXC |CY7C1366C166AXCCYPRESSN/a2avai9-Mbit (256 K ?36/512 K ?18) Pipelined DCD Sync SRAM
CY7C1366C-166AXC |CY7C1366C166AXCCYN/a19avai9-Mbit (256 K ?36/512 K ?18) Pipelined DCD Sync SRAM
CY7C1367C-166AXC |CY7C1367C166AXCCYPRESS/PBFN/a209avai9-Mbit (256 K ?36/512 K ?18) Pipelined DCD Sync SRAM


CY7C1366C-166AXC ,9-Mbit (256 K ?36/512 K ?18) Pipelined DCD Sync SRAMFunctional Description Supports bus operation up to 166 MHz The CY7C1366C/CY7C1367C SRAM integrates ..
CY7C1366C-166AXC ,9-Mbit (256 K ?36/512 K ?18) Pipelined DCD Sync SRAMBlock Diagram – CY7C1366CADDRESSA 0,A1,AREGISTER2A[1:0]MODEQ1ADV BURSTCLK COUNTER ANDLOGICCLR Q0ADS ..
CY7C1366C-166AXC ,9-Mbit (256 K ?36/512 K ?18) Pipelined DCD Sync SRAMCharacteristics . 21Disabling the JTAG Feature ..10 Switching Waveforms ....... 22Test Access Port ..
CY7C1367B-166AC ,9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAMCY7C1366BCY7C1367B9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM[1]
CY7C1367B-166AI ,9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAMBlock Diagram – CY7C1366B (256K x 36)ADDRESSA0,A1,AREGISTER2 A[1:0]MODEQ1ADV BURSTCLKCOUNTER ANDLOG ..
CY7C1367C-166AXC ,9-Mbit (256 K ?36/512 K ?18) Pipelined DCD Sync SRAMCharacteristics and Pin Definitions ...6 Operating Conditions ........ 15Functional Overview ..7 Id ..
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CY7C1366C-166AXC-CY7C1367C-166AXC

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