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CY7C1168KV18-400BZXC |CY7C1168KV18400BZXCCYN/a5avai18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)


CY7C1168KV18-400BZXC ,18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)Functional Description1100 MHz) at 550 MHz The CY7C1168KV18, and CY7C1170KV18 are 1.8 V Available i ..
CY7C1217F-100AC ,1-Mb (32K x 36) Flow-Through Sync SRAMFeaturesfirst address in a burst and increments the address automati-• 32K x 36 common I/O cally fo ..
CY7C1217F-100AC ,1-Mb (32K x 36) Flow-Through Sync SRAMFunctional DescriptionThe CY7C1217F operates from a +3.3V core power supplywhile all outputs may op ..
CY7C1217F-100AC ,1-Mb (32K x 36) Flow-Through Sync SRAMCY7C1217F1-Mbit (32K x 36) Flow-Through Sync SRAM7.5 ns (117-MHz version). A 2-bit on-chip counter ..
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CY7C1231F-100AC ,2-Mb (128K x 18) Flow-through SRAM with NoBL(TM) ArchitectureFunctional Description• Can support up to 117-MHz bus operations with zero The CY7C1231F is a 3.3V, ..
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CY7C1168KV18-400BZXC

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