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CY74FCT646TSOCCYN/a46avaiOctal Registered Bus Transceivers with 3-State Outputs
CY74FCT646TSOCCYPRESSN/a115avaiOctal Registered Bus Transceivers with 3-State Outputs


CY74FCT646TSOC ,Octal Registered Bus Transceivers with 3-State Outputs/sc/package.FUNCTION TABLE‡INPUTS DATA I/OOPERATIONOR FUNCTIONG DIR CPAB CPBA SAB SBA A –A B –B1 8 ..
CY74FCT646TSOC ,Octal Registered Bus Transceivers with 3-State OutputsCY54FCT646T, CY74FCT646T 8-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCCS031A – JULY 1994 – R ..
CY74FCT652ATQCT ,Octal Bus Transceivers and Registers with 3-State OutputsCY74FCT652T 8-BIT REGISTERED TRANSCEIVERWITH 3-STATE OUTPUTSSCCS032B – SEPTEMBER 1994 – REVISED OC ..
CY74FCT652ATQCTG4 ,Octal Bus Transceivers and Registers with 3-State Outputs 24-SSOP -40 to 85/sc/package.FUNCTION TABLEINPUTS DATA I/OOPERATION ORFUNCTIONGAB GBA CPAB CPBA SAB SBA A –A B –B1 8 ..
CY74FCT652ATSOC ,Octal Bus Transceivers and Registers with 3-State OutputsCY74FCT652T 8-BIT REGISTERED TRANSCEIVERWITH 3-STATE OUTPUTSSCCS032B – SEPTEMBER 1994 – REVISED OC ..
CY74FCT652ATSOC ,Octal Bus Transceivers and Registers with 3-State Outputs/sc/package.FUNCTION TABLEINPUTS DATA I/OOPERATION ORFUNCTIONGAB GBA CPAB CPBA SAB SBA A –A B –B1 8 ..
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CY74FCT646TSOC
Octal Registered Bus Transceivers with 3-State Outputs
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times Fully Compatible With TTL Input and
Output Logic Levels
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Independent Register for A and B Buses CY54FCT646T
– 48-mA Output Sink Current
– 12-mA Output Source Current
CY74FCT646T
– 64-mA Output Sink Current
– 32-mA Output Source Current
3-State Outputs
description

The ’FCT646T devices consist of a bus
transceiver circuit with 3-state, D-type flip-flops,
and control circuitry arranged for multiplexed
transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus
is clocked into the registers as the appropriate
clock pin goes to a high logic level. Output-enable (G) and direction (DIR) inputs control the transceiver function.
In the transceiver mode,data present at the high-impedance port can be stored in either the A or B register, or
in both. Select controls (SAB, SBA) can multiplex stored and real-time (transparent mode) data. DIR determines
which bus receives data when G is low. In the isolation mode (G is high), A data can be stored in the B register
and/or B data can be stored in the A register.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DIR47
GND
SBA368122
GND
DIRSABCP CPBASBAV
NC – No internal connection
CY54FCT646T... L PACKAGE
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